MVFR1_EL1, AArch32 Media and VFP Feature Register 1
The MVFR1_EL1 characteristics are:
Purpose
Describes the features provided by the AArch32 Advanced SIMD and Floating-point implementation.
Must be interpreted with MVFR0_EL1 and MVFR2_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
Configuration
AArch64 System register MVFR1_EL1 bits [31:0] are architecturally mapped to AArch32 System register MVFR1[31:0] .
In an implementation where at least one Exception level supports execution in AArch32 state, but there is no support for Advanced SIMD and floating-point operation, this register is RAZ.
Attributes
MVFR1_EL1 is a 64-bit register.
Field descriptions
The MVFR1_EL1 bit assignments are:
When AArch32 is supported at any Exception level:
Bits [63:32]
Reserved, RES0.
SIMDFMAC, bits [31:28]
Advanced SIMD Fused Multiply-Accumulate. Indicates whether the Advanced SIMD implementation provides fused multiply accumulate instructions. Defined values are:
SIMDFMAC | Meaning |
---|---|
0b0000 |
Not implemented. |
0b0001 |
Implemented. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
The Advanced SIMD and floating-point implementations must provide the same level of support for these instructions.
FPHP, bits [27:24]
Floating Point Half Precision. Indicates the level of half-precision floating-point support. Defined values are:
FPHP | Meaning |
---|---|
0b0000 |
Not supported. |
0b0001 |
Floating-point half-precision conversion instructions are supported for conversion between single-precision and half-precision. |
0b0010 |
As for 0b0001, and adds instructions for conversion between double-precision and half-precision. |
0b0011 |
As for 0b0010, and adds support for half-precision floating-point arithmetic. |
All other values are reserved.
In Armv8-A, the permitted values are:
- 0b0000 in an implementation without floating-point support.
- 0b0010 in an implementation with floating-point support that does not include the FEAT_FP16 extension.
- 0b0011 in an implementation with floating-point support that includes the FEAT_FP16 extension.
The level of support indicated by this field must be equivalent to the level of support indicated by the SIMDHP field, meaning the permitted values are:
Half Precision instructions supported | FPHP | SIMDHP |
---|---|---|
No support | 0b0000 | 0b0000 |
Conversions only | 0b0010 | 0b0001 |
Conversions and arithmetic | 0b0011 | 0b0010 |
SIMDHP, bits [23:20]
Advanced SIMD Half Precision. Indicates the level of half-precision floating-point support. Defined values are:
SIMDHP | Meaning |
---|---|
0b0000 |
Not supported. |
0b0001 |
SIMD half-precision conversion instructions are supported for conversion between single-precision and half-precision. |
0b0010 |
As for 0b0001, and adds support for half-precision floating-point arithmetic. |
All other values are reserved.
In Armv8-A, the permitted values are:
- 0b0000 in an implementation without SIMD floating-point support.
- 0b0010 in an implementation with SIMD floating-point support that does not include the FEAT_FP16 extension.
- 0b0011 in an implementation with SIMD floating-point support that includes the FEAT_FP16 extension.
The level of support indicated by this field must be equivalent to the level of support indicated by the FPHP field, meaning the permitted values are:
Half Precision instructions supported | FPHP | SIMDHP |
---|---|---|
No support | 0b0000 | 0b0000 |
Conversions only | 0b0010 | 0b0001 |
Conversions and arithmetic | 0b0011 | 0b0010 |
SIMDSP, bits [19:16]
Advanced SIMD Single Precision. Indicates whether the Advanced SIMD and floating-point implementation provides single-precision floating-point instructions. Defined values are:
SIMDSP | Meaning |
---|---|
0b0000 |
Not implemented. |
0b0001 |
Implemented. This value is permitted only if the SIMDInt field is 0b0001. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
SIMDInt, bits [15:12]
Advanced SIMD Integer. Indicates whether the Advanced SIMD and floating-point implementation provides integer instructions. Defined values are:
SIMDInt | Meaning |
---|---|
0b0000 |
Not implemented. |
0b0001 |
Implemented. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
SIMDLS, bits [11:8]
Advanced SIMD Load/Store. Indicates whether the Advanced SIMD and floating-point implementation provides load/store instructions. Defined values are:
SIMDLS | Meaning |
---|---|
0b0000 |
Not implemented. |
0b0001 |
Implemented. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
FPDNaN, bits [7:4]
Default NaN mode. Indicates whether the floating-point implementation provides support only for the Default NaN mode. Defined values are:
FPDNaN | Meaning |
---|---|
0b0000 |
Not implemented, or hardware supports only the Default NaN mode. |
0b0001 |
Hardware supports propagation of NaN values. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
FPFtZ, bits [3:0]
Flush to Zero mode. Indicates whether the floating-point implementation provides support only for the Flush-to-Zero mode of operation. Defined values are:
FPFtZ | Meaning |
---|---|
0b0000 |
Not implemented, or hardware supports only the Flush-to-Zero mode of operation. |
0b0001 |
Hardware supports full denormalized number arithmetic. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0001.
Otherwise:
Bits [63:0]
Reserved, UNKNOWN.
Accessing the MVFR1_EL1
Accesses to this register use the following encodings:
MRS <Xt>, MVFR1_EL1
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0011 | 0b001 |
if PSTATE.EL == EL0 then if IsFeatureImplemented("FEAT_IDST") then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return MVFR1_EL1; elsif PSTATE.EL == EL2 then return MVFR1_EL1; elsif PSTATE.EL == EL3 then return MVFR1_EL1;