MVFR2_EL1, AArch32 Media and VFP Feature Register 2
The MVFR2_EL1 characteristics are:
Purpose
Describes the features provided by the AArch32 Advanced SIMD and Floating-point implementation.
Must be interpreted with MVFR0_EL1 and MVFR1_EL1.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
Configuration
AArch64 System register MVFR2_EL1 bits [31:0] are architecturally mapped to AArch32 System register MVFR2[31:0] .
In an implementation where at least one Exception level supports execution in AArch32 state, but there is no support for Advanced SIMD and floating-point operation, this register is RAZ.
Attributes
MVFR2_EL1 is a 64-bit register.
Field descriptions
The MVFR2_EL1 bit assignments are:
When AArch32 is supported at any Exception level:
Bits [63:8]
Reserved, RES0.
FPMisc, bits [7:4]
Indicates whether the floating-point implementation provides support for miscellaneous VFP features.
FPMisc | Meaning |
---|---|
0b0000 |
Not implemented, or no support for miscellaneous features. |
0b0001 |
Support for Floating-point selection. |
0b0010 |
As 0b0001, and Floating-point Conversion to Integer with Directed Rounding modes. |
0b0011 |
As 0b0010, and Floating-point Round to Integer Floating-point. |
0b0100 |
As 0b0011, and Floating-point MaxNum and MinNum. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0100.
SIMDMisc, bits [3:0]
Indicates whether the Advanced SIMD implementation provides support for miscellaneous Advanced SIMD features.
SIMDMisc | Meaning |
---|---|
0b0000 |
Not implemented, or no support for miscellaneous features. |
0b0001 |
Floating-point Conversion to Integer with Directed Rounding modes. |
0b0010 |
As 0b0001, and Floating-point Round to Integer Floating-point. |
0b0011 |
As 0b0010, and Floating-point MaxNum and MinNum. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0011.
Otherwise:
Bits [63:0]
Reserved, UNKNOWN.
Accessing the MVFR2_EL1
Accesses to this register use the following encodings:
MRS <Xt>, MVFR2_EL1
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0011 | 0b010 |
if PSTATE.EL == EL0 then if IsFeatureImplemented("FEAT_IDST") then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return MVFR2_EL1; elsif PSTATE.EL == EL2 then return MVFR2_EL1; elsif PSTATE.EL == EL3 then return MVFR2_EL1;