PMBIDR_EL1, Profiling Buffer ID Register
The PMBIDR_EL1 characteristics are:
Purpose
Provides information to software as to whether the buffer can be programmed at the current Exception level.
Configuration
This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMBIDR_EL1 are UNDEFINED.
Attributes
PMBIDR_EL1 is a 64-bit register.
Field descriptions
The PMBIDR_EL1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | F | P | Align | ||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:6]
Reserved, RES0.
F, bit [5]
Flag updates. Defines whether the address translation performed by the Profiling Buffer manages the Access Flag and dirty state.
| F | Meaning |
|---|---|
| 0b0 |
Hardware management of the Access Flag and dirty state for accesses made by the Statistical Profiling Extension is always disabled for all translation stages. |
| 0b1 |
Hardware management for the Access Flag and dirty state for accesses made by the Statistical Profiling Extension is controlled in the same way as explicit memory accesses in the owning translation regime. |
If hardware management of the Access Flag is disabled for a stage of translation, an access to Page or Block with the Access flag bit not set in the descriptor will generate an Access Flag fault.
If hardware management of the dirty state is disabled for a stage of translation, an access to a Page or Block will ignore the Dirty Bit Modifier in the descriptor might generate a Permission fault, depending on the values of the access permission bits in the descriptor.
P, bit [4]
Programming not allowed. The Profiling Buffer is owned by a higher Exception level or the other Security state.
| P | Meaning |
|---|---|
| 0b0 |
Profiling Buffer is owned by the current or a lower Exception level in the current Security state. |
| 0b1 |
Profiling Buffer is owned by a higher Exception level or the other Security state. |
The value read from this field depends on the current Exception level and the Effective values of MDCR_EL3.NSPB and MDCR_EL2.E2PB:
- If EL3 is implemented, and either MDCR_EL3.NSPB == 0b00 or MDCR_EL3.NSPB == 0b01, this bit reads as one from:
- Non-secure EL1.
- Non-secure EL2.
- If Secure EL2 is implemented and enabled, and MDCR_EL2.E2PB == 0b00, Secure EL1.
- If EL3 is implemented, and either MDCR_EL3.NSPB == 0b10 or MDCR_EL3.NSPB == 0b11, this bit reads as one from:
- Secure EL1.
- If Secure EL2 is implemented, Secure EL2.
- If EL2 is implemented and MDCR_EL2.E2PB == 0b00, Non-secure EL1.
- If EL3 is not implemented, EL2 is implemented, and MDCR_EL2.E2PB == 0b00, this bit reads as one from EL1.
- Otherwise, this bit reads as zero.
Align, bits [3:0]
Defines the minimum alignment constraint for PMBPTR_EL1. If this field is non-zero, then the PE must pad every record up to a multiple of this size.
| Align | Meaning |
|---|---|
| 0b0000 |
Byte |
| 0b0001 |
Halfword. |
| 0b0010 |
Word. |
| 0b0011 |
Doubleword. |
| 0b0100 |
16 Bytes. |
| 0b0101 |
32 Bytes. |
| 0b0110 |
64 Bytes. |
| 0b0111 |
128 Bytes. |
| 0b1000 |
256 Bytes. |
| 0b1001 |
512 Bytes. |
| 0b1010 |
1KB. |
| 0b1011 |
2KB. |
For more information, see 'Restrictions on the current write pointer'.
Accessing the PMBIDR_EL1
Accesses to this register use the following encodings:
MRS <Xt>, PMBIDR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1010 | 0b111 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
return PMBIDR_EL1;
elsif PSTATE.EL == EL2 then
return PMBIDR_EL1;
elsif PSTATE.EL == EL3 then
return PMBIDR_EL1;