PMCCFILTR_EL0, Performance Monitors Cycle Count Filter Register
The PMCCFILTR_EL0 characteristics are:
Purpose
Determines the modes in which the Cycle Counter, PMCCNTR_EL0, increments.
Configuration
AArch64 System register PMCCFILTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCCFILTR[31:0] .
AArch64 System register PMCCFILTR_EL0 bits [31:0] are architecturally mapped to External register PMCCFILTR_EL0[31:0] .
This register is present only when FEAT_PMUv3 is implemented. Otherwise, direct accesses to PMCCFILTR_EL0 are UNDEFINED.
Attributes
PMCCFILTR_EL0 is a 64-bit register.
Field descriptions
The PMCCFILTR_EL0 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| P | U | NSK | NSU | NSH | M | RES0 | SH | RES0 | |||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:32]
Reserved, RES0.
P, bit [31]
Privileged filtering bit. Controls counting in EL1.
If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the PMCCFILTR_EL0.NSK bit.
| P | Meaning |
|---|---|
| 0b0 |
Count cycles in EL1. |
| 0b1 |
Do not count cycles in EL1. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
U, bit [30]
User filtering bit. Controls counting in EL0.
If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the PMCCFILTR_EL0.NSU bit.
| U | Meaning |
|---|---|
| 0b0 |
Count cycles in EL0. |
| 0b1 |
Do not count cycles in EL0. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
NSK, bit [29]
When EL3 is implemented:
When EL3 is implemented:
Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.P bit, cycles in Non-secure EL1 are counted.
Otherwise, cycles in Non-secure EL1 are not counted.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
NSU, bit [28]
When EL3 is implemented:
When EL3 is implemented:
Non-secure EL0 (Unprivileged) filtering bit. Controls counting in Non-secure EL0.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.U bit, cycles in Non-secure EL0 are counted.
Otherwise, cycles in Non-secure EL0 are not counted.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
NSH, bit [27]
When EL2 is implemented:
When EL2 is implemented:
EL2 (Hypervisor) filtering bit. Controls counting in EL2.
If Secure EL2 is implemented, and EL3 is implemented, counting in Secure EL2 is further controlled by the PMCCFILTR_EL0.SH bit.
| NSH | Meaning |
|---|---|
| 0b0 |
Do not count cycles in EL2. |
| 0b1 |
Count cycles in EL2. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
M, bit [26]
When EL3 is implemented:
When EL3 is implemented:
Secure EL3 filtering bit.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.P bit, cycles in Secure EL3 are counted.
Otherwise, cycles in Secure EL3 are not counted.
Most applications can ignore this field and set its value to 0.
This field is not visible in the AArch32 PMCCFILTR System register.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
Bit [25]
Reserved, RES0.
SH, bit [24]
When FEAT_SEL2 is implemented and EL3 is implemented:
When FEAT_SEL2 is implemented and EL3 is implemented:
Secure EL2 filtering.
If the value of this bit is not equal to the value of the PMCCFILTR_EL0.NSH bit, cycles in Secure EL2 are counted.
Otherwise, cycles in Secure EL2 are not counted.
If Secure EL2 is not implemented or is disabled, this field is RES0.
This field is not visible in the AArch32 PMCCFILTR System register.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
Bits [23:0]
Reserved, RES0.
Accessing the PMCCFILTR_EL0
PMCCFILTR_EL0 can also be accessed by using PMXEVTYPER_EL0 with PMSELR_EL0.SEL set to 0b11111.
Accesses to this register use the following encodings:
MRS <Xt>, PMCCFILTR_EL0
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b1110 | 0b1111 | 0b111 |
if PSTATE.EL == EL0 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then
UNDEFINED;
elsif PMUSERENR_EL0.EN == '0' then
if EL2Enabled() && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMCCFILTR_EL0 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && MDCR_EL2.TPM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return PMCCFILTR_EL0;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then
UNDEFINED;
elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMCCFILTR_EL0 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && MDCR_EL2.TPM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return PMCCFILTR_EL0;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then
UNDEFINED;
elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return PMCCFILTR_EL0;
elsif PSTATE.EL == EL3 then
return PMCCFILTR_EL0;
MSR PMCCFILTR_EL0, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b1110 | 0b1111 | 0b111 |
if PSTATE.EL == EL0 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then
UNDEFINED;
elsif PMUSERENR_EL0.EN == '0' then
if EL2Enabled() && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMCCFILTR_EL0 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && MDCR_EL2.TPM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
PMCCFILTR_EL0 = X[t];
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then
UNDEFINED;
elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMCCFILTR_EL0 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && MDCR_EL2.TPM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
PMCCFILTR_EL0 = X[t];
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then
UNDEFINED;
elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
PMCCFILTR_EL0 = X[t];
elsif PSTATE.EL == EL3 then
PMCCFILTR_EL0 = X[t];