PMCEID0_EL0, Performance Monitors Common Event Identification register 0
The PMCEID0_EL0 characteristics are:
Purpose
Defines which common architectural events and common microarchitectural events are implemented, or counted, using PMU events in the ranges 0x0000 to 0x001F and 0x4000 to 0x401F.
When the value of a bit in the register is 1 the corresponding common event is implemented and counted.
Arm recommends that, if a common event is never counted, the value of the corresponding register bit is 0.
For more information about the common events and the use of the PMCEID<n>_EL0 registers see 'The PMU event number space and common events'.
Configuration
AArch64 System register PMCEID0_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCEID0[31:0] .
AArch64 System register PMCEID0_EL0 bits [63:32] are architecturally mapped to AArch32 System register PMCEID2[31:0] .
AArch64 System register PMCEID0_EL0 bits [31:0] are architecturally mapped to External register PMCEID0[31:0] .
AArch64 System register PMCEID0_EL0 bits [63:32] are architecturally mapped to External register PMCEID2[31:0] .
This register is present only when FEAT_PMUv3 is implemented. Otherwise, direct accesses to PMCEID0_EL0 are UNDEFINED.
Attributes
PMCEID0_EL0 is a 64-bit register.
Field descriptions
The PMCEID0_EL0 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| IDhi<n>, bit [n+32], for n = 0 to 31 | |||||||||||||||||||||||||||||||
| ID31 | ID30 | ID29 | ID28 | ID27 | ID26 | ID25 | ID24 | ID23 | ID22 | ID21 | ID20 | ID19 | ID18 | ID17 | ID16 | ID15 | ID14 | ID13 | ID12 | ID11 | ID10 | ID9 | ID8 | ID7 | ID6 | ID5 | ID4 | ID3 | ID2 | ID1 | ID0 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDhi<n>, bit [n+32], for n = 0 to 31
When FEAT_PMUv3p1 is implemented:
When FEAT_PMUv3p1 is implemented:
IDhi[n] corresponds to common event (0x4000 + n).
For each bit:
| IDhi<n> | Meaning |
|---|---|
| 0b0 |
The common event is not implemented, or not counted. |
| 0b1 |
The common event is implemented. |
A bit that corresponds to a reserved event number is reserved. The value might be used in a future revision of the architecture to identify an additional common event.
Such an event might be added retrospectively to an earlier version of the PMU architecture, provided the event does not require any additional PMU features and has an event number that can be represented in the PMCEID<n>_EL0 registers of that earlier version of the PMU architecture.
Otherwise:
Otherwise:
Reserved, RES0.
ID<n>, bit [n], for n = 0 to 31
ID[n] corresponds to common event n.
For each bit:
| ID<n> | Meaning |
|---|---|
| 0b0 |
The common event is not implemented, or not counted. |
| 0b1 |
The common event is implemented. |
A bit that corresponds to a reserved event number is reserved. The value might be used in a future revision of the architecture to identify an additional common event.
Such an event might be added retrospectively to an earlier version of the PMU architecture, provided the event does not require any additional PMU features and has an event number that can be represented in the PMCEID<n>_EL0 registers of that earlier version of the PMU architecture.
Accessing the PMCEID0_EL0
Accesses to this register use the following encodings:
MRS <Xt>, PMCEID0_EL0
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b1001 | 0b1100 | 0b110 |
if PSTATE.EL == EL0 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then
UNDEFINED;
elsif PMUSERENR_EL0.EN == '0' then
if EL2Enabled() && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && MDCR_EL2.TPM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return PMCEID0_EL0;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then
UNDEFINED;
elsif EL2Enabled() && MDCR_EL2.TPM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return PMCEID0_EL0;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then
UNDEFINED;
elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return PMCEID0_EL0;
elsif PSTATE.EL == EL3 then
return PMCEID0_EL0;