RVBAR_EL1, Reset Vector Base Address Register (if EL2 and EL3 not implemented)
The RVBAR_EL1 characteristics are:
Purpose
If EL1 is the highest Exception level implemented, contains the IMPLEMENTATION DEFINED address that execution starts from after reset when executing in AArch64 state.
Configuration
This register is present only when the highest implemented Exception level is EL1. Otherwise, direct accesses to RVBAR_EL1 are UNDEFINED.
Attributes
RVBAR_EL1 is a 64-bit register.
Field descriptions
The RVBAR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Reset Address | |||||||||||||||||||||||||||||||
Reset Address | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:0]
Reset Address. The IMPLEMENTATION DEFINED address that execution starts from after reset when executing in 64-bit state. Bits[1:0] of this register are 00, as this address must be aligned, and the address must be within the physical address size supported by the PE.
Accessing the RVBAR_EL1
Accesses to this register use the following encodings:
MRS <Xt>, RVBAR_EL1
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1100 | 0b0000 | 0b001 |
if PSTATE.EL == EL1 && IsHighestEL(EL1) then return RVBAR_EL1; else UNDEFINED;