TCR_EL1, Translation Control Register (EL1)
The TCR_EL1 characteristics are:
Purpose
The control register for stage 1 of the EL1&0 translation regime.
Configuration
AArch64 System register TCR_EL1 bits [31:0] are architecturally mapped to AArch32 System register TTBCR[31:0] .
AArch64 System register TCR_EL1 bits [63:32] are architecturally mapped to AArch32 System register TTBCR2[31:0] .
Attributes
TCR_EL1 is a 64-bit register.
Field descriptions
The TCR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | TCMA1 | TCMA0 | E0PD1 | E0PD0 | NFD1 | NFD0 | TBID1 | TBID0 | HWU162 | HWU161 | HWU160 | HWU159 | HWU062 | HWU061 | HWU060 | HWU059 | HPD1 | HPD0 | HD | HA | TBI1 | TBI0 | AS | RES0 | IPS | ||||||
TG1 | SH1 | ORGN1 | IRGN1 | EPD1 | A1 | T1SZ | TG0 | SH0 | ORGN0 | IRGN0 | EPD0 | RES0 | T0SZ | ||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Any of the bits in TCR_EL1, other than the A1 bit and the EPDx bits when they have the value 1, are permitted to be cached in a TLB.
Bits [63:59]
Reserved, RES0.
TCMA1, bit [58]
When FEAT_MTE is implemented:
When FEAT_MTE is implemented:
Controls the generation of Unchecked accesses at EL1, and at EL0 if HCR_EL2.{E2H,TGE}!={1,1}, when address[59:55] = 0b11111.
TCMA1 | Meaning |
---|---|
0b0 |
This control has no effect on the generation of Unchecked accesses at EL1 or EL0. |
0b1 |
All accesses at EL1 and EL0 are Unchecked. |
Software may change this control bit on a context switch.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
TCMA0, bit [57]
When FEAT_MTE is implemented:
When FEAT_MTE is implemented:
Controls the generation of Unchecked accesses at EL1, and at EL0 if HCR_EL2.{E2H,TGE}!={1,1}, when address[59:55] = 0b00000.
TCMA0 | Meaning |
---|---|
0b0 |
This control has no effect on the generation of Unchecked accesses at EL1 or EL0. |
0b1 |
All accesses at EL1 and EL0 are Unchecked. |
Software may change this control bit on a context switch.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
E0PD1, bit [56]
When FEAT_E0PD is implemented:
When FEAT_E0PD is implemented:
Faulting control for Unprivileged access to any address translated by TTBR1_EL1.
E0PD1 | Meaning |
---|---|
0b0 |
Unprivileged access to any address translated by TTBR1_EL1 will not generate a fault by this mechanism. |
0b1 |
Unprivileged access to any address translated by TTBR1_EL1 will generate a level 0 translation fault |
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
E0PD0, bit [55]
When FEAT_E0PD is implemented:
When FEAT_E0PD is implemented:
Faulting control for Unprivileged access to any address translated by TTBR0_EL1.
E0PD0 | Meaning |
---|---|
0b0 |
Unprivileged access to any address translated by TTBR0_EL1 will not generate a fault by this mechanism. |
0b1 |
Unprivileged access to any address translated by TTBR0_EL1 will generate a level 0 translation fault |
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
NFD1, bit [54]
When FEAT_SVE is implemented:
When FEAT_SVE is implemented:
Non-fault translation table walk disable for stage 1 translations using TTBR1_EL1.
This bit controls whether to perform a stage 1 translation table walk in response to a non-fault unprivileged access for a virtual address that is translated using TTBR1_EL1.
If SVE is implemented, the affected access types include:
- All accesses due to an SVE non-fault contiguous load instruction.
- Accesses due to an SVE first-fault gather load instruction that are not for the First active element. Accesses due to an SVE first-fault contiguous load instruction are not affected.
- Accesses due to prefetch instructions might be affected, but the effect is not architecturally visible.
For more information, see 'The Scalable Vector Extension (SVE)'.
NFD1 | Meaning |
---|---|
0b0 |
Does not disable stage 1 translation table walks using TTBR1_EL1. |
0b1 |
A TLB miss on a virtual address that is translated using TTBR1_EL1 due to the specified access types causes the access to fail without taking an exception. No stage 1 translation table walk is performed. |
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
NFD0, bit [53]
When FEAT_SVE is implemented:
When FEAT_SVE is implemented:
Non-fault translation table walk disable for stage 1 translations using TTBR0_EL1.
This bit controls whether to perform a stage 1 translation table walk in response to a non-fault unprivileged access for a virtual address that is translated using TTBR0_EL1.
If SVE is implemented, the affected access types include:
- All accesses due to an SVE non-fault contiguous load instruction.
- Accesses due to an SVE first-fault gather load instruction that are not for the First active element. Accesses due to an SVE first-fault contiguous load instruction are not affected.
- Accesses due to prefetch instructions might be affected, but the effect is not architecturally visible.
For more information, see 'The Scalable Vector Extension (SVE)'.
NFD0 | Meaning |
---|---|
0b0 |
Does not disable stage 1 translation table walks using TTBR0_EL1. |
0b1 |
A TLB miss on a virtual address that is translated using TTBR0_EL1 due to the specified access types causes the access to fail without taking an exception. No stage 1 translation table walk is performed. |
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
TBID1, bit [52]
When FEAT_PAuth is implemented:
When FEAT_PAuth is implemented:
Controls the use of the top byte of instruction addresses for address matching.
For the purpose of this field, all cache maintenance and address translation instructions that perform address translation are treated as data accesses.
For more information, see 'Address tagging in AArch64 state'.
TBID1 | Meaning |
---|---|
0b0 |
TCR_EL1.TBI1 applies to Instruction and Data accesses. |
0b1 |
TCR_EL1.TBI1 applies to Data accesses only. |
This affects addresses where the address would be translated by tables pointed to by TTBR1_EL1.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
TBID0, bit [51]
When FEAT_PAuth is implemented:
When FEAT_PAuth is implemented:
Controls the use of the top byte of instruction addresses for address matching.
For the purpose of this field, all cache maintenance and address translation instructions that perform address translation are treated as data accesses.
For more information, see 'Address tagging in AArch64 state'.
TBID0 | Meaning |
---|---|
0b0 |
TCR_EL1.TBI0 applies to Instruction and Data accesses. |
0b1 |
TCR_EL1.TBI0 applies to Data accesses only. |
This affects addresses where the address would be translated by tables pointed to by TTBR0_EL1.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU162, bit [50]
When FEAT_HPDS2 is implemented:
When FEAT_HPDS2 is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table Block or Page entry for translations using TTBR1_EL1.
HWU162 | Meaning |
---|---|
0b0 |
For translations using TTBR1_EL1, bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
0b1 |
For translations using TTBR1_EL1, bit[62] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TCR_EL1.HPD1 is 1. |
The Effective value of this field is 0 if the value of TCR_EL1.HPD1 is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU161, bit [49]
When FEAT_HPDS2 is implemented:
When FEAT_HPDS2 is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table Block or Page entry for translations using TTBR1_EL1.
HWU161 | Meaning |
---|---|
0b0 |
For translations using TTBR1_EL1, bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
0b1 |
For translations using TTBR1_EL1, bit[61] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TCR_EL1.HPD1 is 1. |
The Effective value of this field is 0 if the value of TCR_EL1.HPD1 is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU160, bit [48]
When FEAT_HPDS2 is implemented:
When FEAT_HPDS2 is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table Block or Page entry for translations using TTBR1_EL1.
HWU160 | Meaning |
---|---|
0b0 |
For translations using TTBR1_EL1, bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
0b1 |
For translations using TTBR1_EL1, bit[60] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TCR_EL1.HPD1 is 1. |
The Effective value of this field is 0 if the value of TCR_EL1.HPD1 is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU159, bit [47]
When FEAT_HPDS2 is implemented:
When FEAT_HPDS2 is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table Block or Page entry for translations using TTBR1_EL1.
HWU159 | Meaning |
---|---|
0b0 |
For translations using TTBR1_EL1, bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
0b1 |
For translations using TTBR1_EL1, bit[59] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TCR_EL1.HPD1 is 1. |
The Effective value of this field is 0 if the value of TCR_EL1.HPD1 is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU062, bit [46]
When FEAT_HPDS2 is implemented:
When FEAT_HPDS2 is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table Block or Page entry for translations using TTBR0_EL1.
HWU062 | Meaning |
---|---|
0b0 |
For translations using TTBR0_EL1, bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
0b1 |
For translations using TTBR0_EL1, bit[62] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TCR_EL1.HPD0 is 1. |
The Effective value of this field is 0 if the value of TCR_EL1.HPD0 is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU061, bit [45]
When FEAT_HPDS2 is implemented:
When FEAT_HPDS2 is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table Block or Page entry for translations using TTBR0_EL1.
HWU061 | Meaning |
---|---|
0b0 |
For translations using TTBR0_EL1, bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
0b1 |
For translations using TTBR0_EL1, bit[61] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TCR_EL1.HPD0 is 1. |
The Effective value of this field is 0 if the value of TCR_EL1.HPD0 is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU060, bit [44]
When FEAT_HPDS2 is implemented:
When FEAT_HPDS2 is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table Block or Page entry for translations using TTBR0_EL1.
HWU060 | Meaning |
---|---|
0b0 |
For translations using TTBR0_EL1, bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
0b1 |
For translations using TTBR0_EL1, bit[60] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TCR_EL1.HPD0 is 1. |
The Effective value of this field is 0 if the value of TCR_EL1.HPD0 is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HWU059, bit [43]
When FEAT_HPDS2 is implemented:
When FEAT_HPDS2 is implemented:
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table Block or Page entry for translations using TTBR0_EL1.
HWU059 | Meaning |
---|---|
0b0 |
For translations using TTBR0_EL1, bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
0b1 |
For translations using TTBR0_EL1, bit[59] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TCR_EL1.HPD0 is 1. |
The Effective value of this field is 0 if the value of TCR_EL1.HPD0 is 0.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HPD1, bit [42]
When FEAT_HPDS is implemented:
When FEAT_HPDS is implemented:
Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, PXNTable, and UXNTable, except NSTable, in the translation tables pointed to by TTBR1_EL1.
HPD1 | Meaning |
---|---|
0b0 |
Hierarchical permissions are enabled. |
0b1 |
Hierarchical permissions are disabled. |
When disabled, the permissions are treated as if the bits are zero.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HPD0, bit [41]
When FEAT_HPDS is implemented:
When FEAT_HPDS is implemented:
Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, PXNTable, and UXNTable, except NSTable, in the translation tables pointed to by TTBR0_EL1.
HPD0 | Meaning |
---|---|
0b0 |
Hierarchical permissions are enabled. |
0b1 |
Hierarchical permissions are disabled. |
When disabled, the permissions are treated as if the bits are zero.
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HD, bit [40]
When FEAT_HAFDBS is implemented:
When FEAT_HAFDBS is implemented:
Hardware management of dirty state in stage 1 translations from EL0 and EL1.
HD | Meaning |
---|---|
0b0 |
Stage 1 hardware management of dirty state disabled. |
0b1 |
Stage 1 hardware management of dirty state enabled, only if the HA bit is also set to 1. |
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
HA, bit [39]
When FEAT_HAFDBS is implemented:
When FEAT_HAFDBS is implemented:
Hardware Access flag update in stage 1 translations from EL0 and EL1.
HA | Meaning |
---|---|
0b0 |
Stage 1 Access flag update disabled. |
0b1 |
Stage 1 Access flag update enabled. |
This field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
TBI1, bit [38]
Top Byte ignored. Indicates whether the top byte of an address is used for address match for the TTBR1_EL1 region, or ignored and used for tagged addresses.
TBI1 | Meaning |
---|---|
0b0 |
Top Byte used in the address calculation. |
0b1 |
Top Byte ignored in the address calculation. |
This affects addresses generated in EL0 and EL1 using AArch64 where the address would be translated by tables pointed to by TTBR1_EL1. It has an effect whether the EL1&0 translation regime is enabled or not.
If FEAT_PAuth is implemented and TCR_EL1.TBID1 is 1, then this field only applies to Data accesses.
Otherwise, if the value of TBI1 is 1 and bit [55] of the target address to be stored to the PC is 1, then bits[63:56] of that target address are also set to 1 before the address is stored in the PC, in the following cases:
- A branch or procedure return within EL0 or EL1.
- An exception taken to EL1.
- An exception return to EL0 or EL1.
This field resets to an architecturally UNKNOWN value.
TBI0, bit [37]
Top Byte ignored. Indicates whether the top byte of an address is used for address match for the TTBR0_EL1 region, or ignored and used for tagged addresses.
TBI0 | Meaning |
---|---|
0b0 |
Top Byte used in the address calculation. |
0b1 |
Top Byte ignored in the address calculation. |
This affects addresses generated in EL0 and EL1 using AArch64 where the address would be translated by tables pointed to by TTBR0_EL1. It has an effect whether the EL1&0 translation regime is enabled or not.
If FEAT_PAuth is implemented and TCR_EL1.TBID0 is 1, then this field only applies to Data accesses.
Otherwise, if the value of TBI0 is 1 and bit [55] of the target address to be stored to the PC is 0, then bits[63:56] of that target address are also set to 0 before the address is stored in the PC, in the following cases:
- A branch or procedure return within EL0 or EL1.
- An exception taken to EL1.
- An exception return to EL0 or EL1.
This field resets to an architecturally UNKNOWN value.
AS, bit [36]
ASID Size.
AS | Meaning |
---|---|
0b0 |
8 bit - the upper 8 bits of TTBR0_EL1 and TTBR1_EL1 are ignored by hardware for every purpose except reading back the register, and are treated as if they are all zeros for when used for allocation and matching entries in the TLB. |
0b1 |
16 bit - the upper 16 bits of TTBR0_EL1 and TTBR1_EL1 are used for allocation and matching in the TLB. |
If the implementation has only 8 bits of ASID, this field is RES0.
This field resets to an architecturally UNKNOWN value.
Bit [35]
Reserved, RES0.
IPS, bits [34:32]
Intermediate Physical Address Size.
IPS | Meaning |
---|---|
0b000 |
32 bits, 4GB. |
0b001 |
36 bits, 64GB. |
0b010 |
40 bits, 1TB. |
0b011 |
42 bits, 4TB. |
0b100 |
44 bits, 16TB. |
0b101 |
48 bits, 256TB. |
0b110 |
52 bits, 4PB. |
All other values are reserved.
The reserved values behave in the same way as the 0b101 or 0b110 encoding, but software must not rely on this property as the behavior of the reserved values might change in a future revision of the architecture.
If the translation granule is not 64KB, the value 0b110 is treated as reserved.
It is IMPLEMENTATION DEFINED whether an implementation that does not implement FEAT_LPA supports setting the value of 0b110 for the 64KB translation granule size or whether setting this value behaves as the 0b101 encoding.
In an implementation that supports 52-bit PAs, if the value of this field is not 0b110 or a value treated as 0b110, then bits[51:48] of every translation table base address for the stage of translation controlled by TCR_EL1 are 0b0000.
This field resets to an architecturally UNKNOWN value.
TG1, bits [31:30]
Granule size for the TTBR1_EL1.
TG1 | Meaning |
---|---|
0b01 |
16KB. |
0b10 |
4KB. |
0b11 |
64KB. |
Other values are reserved.
If the value is programmed to either a reserved value, or a size that has not been implemented, then the hardware will treat the field as if it has been programmed to an IMPLEMENTATION DEFINED choice of the sizes that has been implemented for all purposes other than the value read back from this register.
It is IMPLEMENTATION DEFINED whether the value read back is the value programmed or the value that corresponds to the size chosen.
This field resets to an architecturally UNKNOWN value.
SH1, bits [29:28]
Shareability attribute for memory associated with translation table walks using TTBR1_EL1.
SH1 | Meaning |
---|---|
0b00 |
Non-shareable. |
0b10 |
Outer Shareable. |
0b11 |
Inner Shareable. |
Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE.
This field resets to an architecturally UNKNOWN value.
ORGN1, bits [27:26]
Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1.
ORGN1 | Meaning |
---|---|
0b00 |
Normal memory, Outer Non-cacheable. |
0b01 |
Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable. |
0b10 |
Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable. |
0b11 |
Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable. |
This field resets to an architecturally UNKNOWN value.
IRGN1, bits [25:24]
Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1.
IRGN1 | Meaning |
---|---|
0b00 |
Normal memory, Inner Non-cacheable. |
0b01 |
Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable. |
0b10 |
Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable. |
0b11 |
Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable. |
This field resets to an architecturally UNKNOWN value.
EPD1, bit [23]
Translation table walk disable for translations using TTBR1_EL1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR1_EL1. The encoding of this bit is:
EPD1 | Meaning |
---|---|
0b0 |
Perform translation table walks using TTBR1_EL1. |
0b1 |
A TLB miss on an address that is translated using TTBR1_EL1 generates a Translation fault. No translation table walk is performed. |
This field resets to an architecturally UNKNOWN value.
A1, bit [22]
Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID. The encoding of this bit is:
A1 | Meaning |
---|---|
0b0 |
TTBR0_EL1.ASID defines the ASID. |
0b1 |
TTBR1_EL1.ASID defines the ASID. |
This field resets to an architecturally UNKNOWN value.
T1SZ, bits [21:16]
The size offset of the memory region addressed by TTBR1_EL1. The region size is 2(64-T1SZ) bytes.
The maximum and minimum possible values for T1SZ depend on the level of translation table and the memory translation granule size, as described in the AArch64 Virtual Memory System Architecture chapter.
This field resets to an architecturally UNKNOWN value.
TG0, bits [15:14]
Granule size for the TTBR0_EL1.
TG0 | Meaning |
---|---|
0b00 |
4KB |
0b01 |
64KB |
0b10 |
16KB |
Other values are reserved.
If the value is programmed to either a reserved value, or a size that has not been implemented, then the hardware will treat the field as if it has been programmed to an IMPLEMENTATION DEFINED choice of the sizes that has been implemented for all purposes other than the value read back from this register.
It is IMPLEMENTATION DEFINED whether the value read back is the value programmed or the value that corresponds to the size chosen.
This field resets to an architecturally UNKNOWN value.
SH0, bits [13:12]
Shareability attribute for memory associated with translation table walks using TTBR0_EL1.
SH0 | Meaning |
---|---|
0b00 |
Non-shareable |
0b10 |
Outer Shareable |
0b11 |
Inner Shareable |
Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE.
This field resets to an architecturally UNKNOWN value.
ORGN0, bits [11:10]
Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1.
ORGN0 | Meaning |
---|---|
0b00 |
Normal memory, Outer Non-cacheable. |
0b01 |
Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable. |
0b10 |
Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable. |
0b11 |
Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable. |
This field resets to an architecturally UNKNOWN value.
IRGN0, bits [9:8]
Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1.
IRGN0 | Meaning |
---|---|
0b00 |
Normal memory, Inner Non-cacheable. |
0b01 |
Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable. |
0b10 |
Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable. |
0b11 |
Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable. |
This field resets to an architecturally UNKNOWN value.
EPD0, bit [7]
Translation table walk disable for translations using TTBR0_EL1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR0_EL1. The encoding of this bit is:
EPD0 | Meaning |
---|---|
0b0 |
Perform translation table walks using TTBR0_EL1. |
0b1 |
A TLB miss on an address that is translated using TTBR0_EL1 generates a Translation fault. No translation table walk is performed. |
This field resets to an architecturally UNKNOWN value.
Bit [6]
Reserved, RES0.
T0SZ, bits [5:0]
The size offset of the memory region addressed by TTBR0_EL1. The region size is 2(64-T0SZ) bytes.
The maximum and minimum possible values for T0SZ depend on the level of translation table and the memory translation granule size, as described in the AArch64 Virtual Memory System Architecture chapter.
This field resets to an architecturally UNKNOWN value.
Accessing the TCR_EL1
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic TCR_EL1 or TCR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
Accesses to this register use the following encodings:
MRS <Xt>, TCR_EL1
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0010 | 0b0000 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x120]; else return TCR_EL1; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then return TCR_EL2; else return TCR_EL1; elsif PSTATE.EL == EL3 then return TCR_EL1;
MSR TCR_EL1, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0010 | 0b0000 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x120] = X[t]; else TCR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then TCR_EL2 = X[t]; else TCR_EL1 = X[t]; elsif PSTATE.EL == EL3 then TCR_EL1 = X[t];
MRS <Xt>, TCR_EL12
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b101 | 0b0010 | 0b0000 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then return NVMem[0x120]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then return TCR_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' then return TCR_EL1; else UNDEFINED;
MSR TCR_EL12, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b101 | 0b0010 | 0b0000 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then NVMem[0x120] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then TCR_EL1 = X[t]; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' then TCR_EL1 = X[t]; else UNDEFINED;