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TPIDR_EL3, EL3 Software Thread ID Register
The TPIDR_EL3 characteristics are:
Purpose
Provides a location where software executing at EL3 can store thread identifying information, for OS management purposes.
The PE makes no use of this register.
Configuration
This register is present only when EL3 is implemented. Otherwise, direct accesses to TPIDR_EL3 are UNDEFINED.
Attributes
TPIDR_EL3 is a 64-bit register.
Field descriptions
The TPIDR_EL3 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| Thread ID | |||||||||||||||||||||||||||||||
| Thread ID | |||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:0]
Thread ID. Thread identifying information stored by software running at this Exception level.
This field resets to an architecturally UNKNOWN value.
Accessing the TPIDR_EL3
Accesses to this register use the following encodings:
MRS <Xt>, TPIDR_EL3
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b110 | 0b1101 | 0b0000 | 0b010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
UNDEFINED;
elsif PSTATE.EL == EL2 then
UNDEFINED;
elsif PSTATE.EL == EL3 then
return TPIDR_EL3;
MSR TPIDR_EL3, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b110 | 0b1101 | 0b0000 | 0b010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
UNDEFINED;
elsif PSTATE.EL == EL2 then
UNDEFINED;
elsif PSTATE.EL == EL3 then
TPIDR_EL3 = X[t];