AMCNTENSET0, Activity Monitors Count Enable Set Register 0
The AMCNTENSET0 characteristics are:
Purpose
Enable control bits for the architected activity monitors event counters, AMEVCNTR0<n>.
Configuration
External register AMCNTENSET0 bits [31:0] are architecturally mapped to AArch64 System register AMCNTENSET0_EL0[31:0] .
External register AMCNTENSET0 bits [31:0] are architecturally mapped to AArch32 System register AMCNTENSET0[31:0] .
The power domain of AMCNTENSET0 is IMPLEMENTATION DEFINED.
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCNTENSET0 are RES0.
Attributes
AMCNTENSET0 is a 32-bit register.
Field descriptions
The AMCNTENSET0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P<n>, bit [n] |
P<n>, bit [n], for n = 0 to 31
Activity monitor event counter enable bit for AMEVCNTR0<n>.
Bits [31:N] are RAZ/WI. N is the value in AMCGCR.CG0NC.
Possible values of each bit are:
P<n> | Meaning |
---|---|
0b0 |
When read, means that AMEVCNTR0<n> is disabled. When written, has no effect. |
0b1 |
When read, means that AMEVCNTR0<n> is enabled. When written, enables AMEVCNTR0<n>. |
On a Cold reset, this field resets to 0.
Accessing the AMCNTENSET0
AMCNTENSET0 can be accessed through the memory-mapped interfaces:
Component | Offset | Instance |
---|---|---|
AMU | 0xC00 | AMCNTENSET0 |
Accesses on this interface are RO.