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CTIDEVARCH, CTI Device Architecture register

The CTIDEVARCH characteristics are:


Identifies the programmers' model architecture of the CTI component.


CTIDEVARCH is in the Debug power domain.

If the CTI is CTIv1, this register is OPTIONAL. If the CTI is CTIv2, this register is mandatory.

Arm recommends that the CTI is CTIv2.

In an Armv8.5 compliant implementation, the CTI must be CTIv2.

If this register is not implemented, CTIDEVAFF0 and CTIDEVAFF1 are also not implemented.


CTIDEVARCH is a 32-bit register.

Field descriptions

The CTIDEVARCH bit assignments are:


ARCHITECT, bits [31:21]

Defines the architecture of the component. For CTI, this is Arm Limited.

Bits [31:28] are the JEP106 continuation code, 0x4.

Bits [27:21] are the JEP106 ID code, 0x3B.

PRESENT, bit [20]

When set to 1, indicates that the DEVARCH is present.

This field is 1 in Armv8.

REVISION, bits [19:16]


Defines the architecture revision of the component.

REVISIONMeaningApplies when

First revision.


As 0b0000, and also adds support for CTIDEVCTL.

When FEAT_DoPD is implemented

All other values are reserved.

ARCHID, bits [15:0]

Defines this part to be an Armv8 debug component. For architectures defined by Arm this is further subdivided.

For CTI:

  • Bits [15:12] are the architecture version, 0x1.
  • Bits [11:0] are the architecture part number, 0xA14.

This corresponds to CTI architecture version CTIv2.

Accessing the CTIDEVARCH

CTIDEVARCH can be accessed through the external debug interface:


Accesses on this interface are RO.