DBGDTRRX_EL0, Debug Data Transfer Register, Receive
The DBGDTRRX_EL0 characteristics are:
Transfers data from an external debugger to the PE. For example, it is used by a debugger transferring commands and data to a debug target. See DBGDTR_EL0 for additional architectural mappings. It is a component of the Debug Communications Channel.
External register DBGDTRRX_EL0 bits [31:0] are architecturally mapped to AArch64 System register DBGDTRRX_EL0[31:0] .
External register DBGDTRRX_EL0 bits [31:0] are architecturally mapped to AArch32 System register DBGDTRRXint[31:0] .
DBGDTRRX_EL0 is in the Core power domain.
DBGDTRRX_EL0 is a 32-bit register.
The DBGDTRRX_EL0 bit assignments are:
Writes to this register:
If RXfull is set to 1, set DTRRX to UNKNOWN.
If RXfull is set to 0, update the value in DTRRX.
After the write, RXfull is set to 1.
Reads of this register:
If RXfull is set to 1, return the last value written to DTRRX.
If RXfull is set to 0, return an UNKNOWN value.
After the read, RXfull remains unchanged.
For the full behavior of the Debug Communications Channel, see 'The Debug Communication Channel and Instruction Transfer Register'.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Accessing the DBGDTRRX_EL0
If EDSCR.ITE == 0 when the PE exits Debug state on receiving a Restart request trigger event, the behavior of any operation issued by a DTR access in memory access mode that has not completed execution is CONSTRAINED UNPREDICTABLE, and must do one of the following:
- It must complete execution in Debug state before the PE executes the restart sequence.
- It must complete execution in Non-debug state before the PE executes the restart sequence.
- It must be abandoned. This means that the instruction does not execute. Any registers or memory accessed by the instruction are left in an UNKNOWN state.
DBGDTRRX_EL0 can be accessed through the external debug interface:
This interface is accessible as follows:
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and SoftwareLockStatus() accesses to this register are RO.
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and !SoftwareLockStatus() accesses to this register are RW.
- Otherwise accesses to this register generate an error response.