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EDDFR, External Debug Feature Register

The EDDFR characteristics are:

Purpose

Provides top level information about the debug system.

Note

Debuggers must use EDDEVARCH to determine the Debug architecture version.

For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.

Configuration

It is IMPLEMENTATION DEFINED whether EDDFR is implemented in the Core power domain or in the Debug power domain.

Attributes

EDDFR is a 64-bit register.

Field descriptions

The EDDFR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0TraceFiltUNKNOWN
CTX_CMPsRES0WRPsRES0BRPsPMUVerTraceVerUNKNOWN
313029282726252423222120191817161514131211109876543210

Bits [63:44]

Reserved, RES0.

TraceFilt, bits [43:40]

Armv8.4 Self-hosted Trace Extension version. Defined values are:

TraceFiltMeaning
0b0000

Armv8.4 Self-hosted Trace Extension is not implemented.

0b0001

Armv8.4 Self-hosted Trace Extension is implemented.

All other values are reserved.

FEAT_TRF implements the functionality added by 0b0001.

From Armv8.4, the permitted values are 0b0000 and 0b0001.

Bits [39:32]

Reserved, UNKNOWN.

CTX_CMPs, bits [31:28]

Number of breakpoints that are context-aware, minus 1. These are the highest numbered breakpoints.

In an Armv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.CTX_CMPs.

Bits [27:24]

Reserved, RES0.

WRPs, bits [23:20]

Number of watchpoints, minus 1. The value of 0b0000 is reserved.

In an Armv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.WRPs.

Bits [19:16]

Reserved, RES0.

BRPs, bits [15:12]

Number of breakpoints, minus 1. The value of 0b0000 is reserved.

In an Armv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.BRPs.

PMUVer, bits [11:8]

Performance Monitors Extension version.

This field does not follow the standard ID scheme, but uses the alternative ID scheme described in 'Alternative ID scheme used for the Performance Monitors Extension version'

Defined values are:

PMUVerMeaning
0b0000

Performance Monitors Extension not implemented.

0b0001

Performance Monitors Extension, PMUv3 implemented.

0b0100

PMUv3 for Armv8.1. As 0b0001, and also includes support for:

0b0101

PMUv3 for Armv8.4. As 0b0100, and also includes support for the PMMIR_EL1 register.

0b0110

PMUv3 for Armv8.5. As 0b0101, and also includes support for:

  • 64-bit event counters.
  • If EL2 is implemented, the MDCR_EL2.HCCD control bit.
  • If EL3 is implemented, the MDCR_EL3.SCCD control bit.
0b1111

IMPLEMENTATION DEFINED form of performance monitors supported, PMUv3 not supported. Arm does not recommend this value for new implementations.

All other values are reserved.

FEAT_PMUv3 implements the functionality identified by the value 0b0001.

FEAT_PMUv3p1 implements the functionality identified by the value 0b0100.

FEAT_PMUv3p4 implements the functionality identified by the value 0b0101.

FEAT_PMUv3p5 implements the functionality identified by the value 0b0110.

From Armv8.1, if FEAT_PMUv3 is implemented, the value 0b0001 is not permitted.

From Armv8.4, if FEAT_PMUv3 is implemented, the value 0b0100 is not permitted.

From Armv8.5, if FEAT_PMUv3 is implemented, the value 0b0101 is not permitted.

TraceVer, bits [7:4]

Trace support. Indicates whether System register interface to a PE trace unit is implemented. Defined values are:

TraceVerMeaning
0b0000

PE trace unit System registers not implemented.

0b0001

PE trace unit System registers implemented.

All other values are reserved.

A value of 0b0000 only indicates that no System register interface to a PE trace unit is implemented. A PE trace unit might nevertheless be implemented without a System register interface.

In an Armv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.TraceVer.

Bits [3:0]

Reserved, UNKNOWN.

Accessing the EDDFR

EDDFR can be accessed through the external debug interface:

ComponentOffsetInstanceRange
Debug0xD28EDDFR31:0

This interface is accessible as follows:

  • When IsCorePowered() and !DoubleLockStatus() accesses to this register are RO.
  • Otherwise accesses to this register are IMPDEF.
ComponentOffsetInstanceRange
Debug0xD2CEDDFR63:32

This interface is accessible as follows:

  • When IsCorePowered() and !DoubleLockStatus() accesses to this register are RO.
  • Otherwise accesses to this register are IMPDEF.