EDECCR, External Debug Exception Catch Control Register

The EDECCR characteristics are:

Purpose

Controls Exception Catch debug events.

Configuration

External register EDECCR bits [31:0] are architecturally mapped to AArch64 System register OSECCR_EL1[31:0] .

External register EDECCR bits [31:0] are architecturally mapped to AArch32 System register DBGOSECCR[31:0] .

EDECCR is in the Core power domain.

Attributes

EDECCR is a 32-bit register.

Field descriptions

The EDECCR bit assignments are:

When FEAT_Debugv8p2 is implemented:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																NSR3	NSR2	NSR1	NSR0	SR3	SR2	SR1	SR0	NSE3	NSE2	NSE1	NSE0	SE3	SE2	SE1	SE0

Bits [31:16]

Reserved, RES0.

NSR<n>, bit [n+12], for n = 0 to 3

Controls Non-secure exception catch on exception return to EL<n> in conjunction with NSE<n>. For information, see 'Summary of Exception Catch debug event control'.

If EL3 is not implemented and the PE behaves as if SCR_EL3.NS is set to 0, this field is reserved, RES0.

A value of the NSR field that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If the NSR field is programmed with a reserved value then:

• The PE behaves as if it is programmed with a defined value, other than for a read of EDECCR.
• The value returned for NSR by a read of EDECCR is UNKNOWN.

On a Cold reset, this field resets to 0.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.

SR<n>, bit [n+8], for n = 0 to 3

Controls Secure exception catch on exception return to EL<n> in conjunction with SE<n>. For information, see 'Summary of Exception Catch debug event control'.

If EL3 is not implemented and the PE behaves as if SCR_EL3.NS is set to 1, this field is reserved, RES0.

A value of the SR field that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If the SR field is programmed with a reserved value then:

• The PE behaves as if it is programmed with a defined value, other than for a read of EDECCR.
• The value returned for SR by a read of EDECCR is UNKNOWN.

On a Cold reset, this field resets to 0.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.

NSE<n>, bit [n+4], for n = 0 to 3

Coarse-grained Non-secure exception catch for EL<n>. This controls whether Exception Catch debug events are enabled for Non-secure EL<n>. This also controls:

• The behavior of exception catch on exception entry to EL<n>.
• The behavior of exception catch on exception return to EL<n> in conjunction with NSR<n>.

If EL3 is not implemented and the PE behaves as if SCR_EL3.NS is set to 0, this field is reserved, RES0.

A value of the NSE field that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If the NSE field is programmed with a reserved value then:

• The PE behaves as if it is programmed with a defined value, other than for a read of EDECCR.
• The value returned for NSE by a read of EDECCR is UNKNOWN.

On a Cold reset, this field resets to 0.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.

SE<n>, bit [n], for n = 0 to 3

Coarse-grained Secure exception catch for EL<n>. This field controls whether Exception Catch debug events are enabled for Secure EL<n>.

• The behavior of exception catch on exception entry to EL<n>.
• The behavior of exception catch on exception return to EL<n> in conjunction with SR<n>.

If EL3 is not implemented and the PE behaves as if SCR_EL3.NS is set to 1, this field is reserved, RES0.

A value of the SE field that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If the SE field is programmed with a reserved value then:

• The PE behaves as if it is programmed with a defined value, other than for a read of EDECCR.
• The value returned for SE by a read of EDECCR is UNKNOWN.

On a Cold reset, this field resets to 0.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.

Otherwise:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								NSE3	NSE2	NSE1	NSE0	SE3	SE2	SE1	SE0

Bits [31:8]

Reserved, RES0.

NSE<n>, bit [n+4], for n = 0 to 3

Coarse-grained Non-secure exception catch. If EL3 and EL2 are not implemented and the PE behaves as if SCR_EL3.NS is set to 0, this field is reserved, RES0. Otherwise, possible values for this field are:

A value of the NSE field that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If the NSE field is programmed with a reserved value then:

• The PE behaves as if it is programmed with a defined value, other than for a read of EDECCR.
• The value returned for NSE by a read of EDECCR is UNKNOWN.

On a Cold reset, this field resets to 0.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.

SE<n>, bit [n], for n = 0 to 3

Coarse-grained Secure exception catch.

If EL3 is not implemented and the PE behaves as if SCR_EL3.NS is set to 1, this field is reserved, RES0.

A value of the SE field that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If the SE field is programmed with a reserved value then:

• The PE behaves as if it is programmed with a defined value, other than for a read of EDECCR.
• The value returned for SE by a read of EDECCR is UNKNOWN.

On a Cold reset, this field resets to 0.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.

Accessing the EDECCR

EDECCR can be accessed through the external debug interface:

This interface is accessible as follows:

• When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and SoftwareLockStatus() accesses to this register are RO.
• When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and !SoftwareLockStatus() accesses to this register are RW.
• Otherwise accesses to this register generate an error response.