EDECCR, External Debug Exception Catch Control Register
The EDECCR characteristics are:
Purpose
Controls Exception Catch debug events.
Configuration
External register EDECCR bits [31:0] are architecturally mapped to AArch64 System register OSECCR_EL1[31:0] .
External register EDECCR bits [31:0] are architecturally mapped to AArch32 System register DBGOSECCR[31:0] .
EDECCR is in the Core power domain.
Attributes
EDECCR is a 32-bit register.
Field descriptions
The EDECCR bit assignments are:
When FEAT_Debugv8p2 is implemented:
Bits [31:16]
Reserved, RES0.
NSR<n>, bit [n+12], for n = 0 to 3
Controls Non-secure exception catch on exception return to EL<n> in conjunction with NSE<n>. For information, see 'Summary of Exception Catch debug event control'.
NSR<n> | Meaning |
---|---|
0b0 |
If the corresponding NSE<n> bit is 0, then Exception Catch debug events are disabled for Non-secure Exception level <n>. If the corresponding NSE<n> bit is 1, then Exception Catch debug events are enabled for exception entry, reset entry and exception return to Non-secure Exception level <n>. |
0b1 |
If the corresponding NSE<n> bit is 0, then Exception Catch debug events are enabled for exception returns to Non-secure Exception level <n>. If the corresponding NSE<n> bit is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Non-secure Exception level <n>. |
If EL3 is not implemented and the PE behaves as if SCR_EL3.NS is set to 0, this field is reserved, RES0.
It is IMPLEMENTATION DEFINED whether a reset entry to an Exception level is permitted to generate an Exception Catch debug event.
A value of the NSR field that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If the NSR field is programmed with a reserved value then:
- The PE behaves as if it is programmed with a defined value, other than for a read of EDECCR.
- The value returned for NSR by a read of EDECCR is UNKNOWN.
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
SR<n>, bit [n+8], for n = 0 to 3
Controls Secure exception catch on exception return to EL<n> in conjunction with SE<n>. For information, see 'Summary of Exception Catch debug event control'.
SR<n> | Meaning |
---|---|
0b0 |
If the corresponding SE<n> bit is 0, then Exception Catch debug events are disabled for Secure Exception level <n>. If the corresponding SE<n> bit is 1, then Exception Catch debug events are enabled for exception entry, reset entry and exception return to Secure Exception level <n>. |
0b1 |
If the corresponding SE<n> bit is 0, then Exception Catch debug events are enabled for exception returns to Secure Exception level <n>. If the corresponding SE<n> bit is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Secure Exception level <n>. |
If EL3 is not implemented and the PE behaves as if SCR_EL3.NS is set to 1, this field is reserved, RES0.
It is IMPLEMENTATION DEFINED whether a reset entry to an Exception level is permitted to generate an Exception Catch debug event.
A value of the SR field that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If the SR field is programmed with a reserved value then:
- The PE behaves as if it is programmed with a defined value, other than for a read of EDECCR.
- The value returned for SR by a read of EDECCR is UNKNOWN.
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
NSE<n>, bit [n+4], for n = 0 to 3
Coarse-grained Non-secure exception catch for EL<n>. This controls whether Exception Catch debug events are enabled for Non-secure EL<n>. This also controls:
- The behavior of exception catch on exception entry to EL<n>.
- The behavior of exception catch on exception return to EL<n> in conjunction with NSR<n>.
NSE<n> | Meaning |
---|---|
0b0 |
If the corresponding NSR<n> bit is 0, then Exception Catch debug events are disabled for Non-secure Exception level <n>. If the corresponding NSR<n> bit is 1, then Exception Catch debug events are enabled for exception returns to Non-secure Exception level <n>. |
0b1 |
If the corresponding NSR<n> bit is 0, then Exception Catch debug events are enabled for exception entry, reset entry and exception return to Non-secure Exception level <n>. If the corresponding NSR<n> bit is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Non-secure Exception level <n>. |
If EL3 is not implemented and the PE behaves as if SCR_EL3.NS is set to 0, this field is reserved, RES0.
A value of the NSE field that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If the NSE field is programmed with a reserved value then:
- The PE behaves as if it is programmed with a defined value, other than for a read of EDECCR.
- The value returned for NSE by a read of EDECCR is UNKNOWN.
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
SE<n>, bit [n], for n = 0 to 3
Coarse-grained Secure exception catch for EL<n>. This field controls whether Exception Catch debug events are enabled for Secure EL<n>.
- The behavior of exception catch on exception entry to EL<n>.
- The behavior of exception catch on exception return to EL<n> in conjunction with SR<n>.
SE<n> | Meaning |
---|---|
0b0 |
If the corresponding SR<n> bit is 0, then Exception Catch debug events are disabled for Secure Exception level <n>. If the corresponding SR<n> bit is 1, then Exception Catch debug events are enabled for exception returns to Secure Exception level <n>. |
0b1 |
If the corresponding SR<n> bit is 0, then Exception Catch debug events are enabled for exception entry, reset entry and exception return to Secure Exception level <n>. If the corresponding SR<n> bit is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Secure Exception level <n>. |
If EL3 is not implemented and the PE behaves as if SCR_EL3.NS is set to 1, this field is reserved, RES0.
A value of the SE field that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If the SE field is programmed with a reserved value then:
- The PE behaves as if it is programmed with a defined value, other than for a read of EDECCR.
- The value returned for SE by a read of EDECCR is UNKNOWN.
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Otherwise:
Bits [31:8]
Reserved, RES0.
NSE<n>, bit [n+4], for n = 0 to 3
Coarse-grained Non-secure exception catch. If EL3 and EL2 are not implemented and the PE behaves as if SCR_EL3.NS is set to 0, this field is reserved, RES0. Otherwise, possible values for this field are:
NSE<n> | Meaning |
---|---|
0b0 |
Exception Catch debug events are disabled for Non-secure Exception level <n>. |
0b1 |
Exception Catch debug events are enabled for Non-secure Exception level <n>. |
A value of the NSE field that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If the NSE field is programmed with a reserved value then:
- The PE behaves as if it is programmed with a defined value, other than for a read of EDECCR.
- The value returned for NSE by a read of EDECCR is UNKNOWN.
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
SE<n>, bit [n], for n = 0 to 3
Coarse-grained Secure exception catch.
SE<n> | Meaning |
---|---|
0b0 |
Exception Catch debug events are disabled for Secure Exception level <n>. |
0b1 |
Exception Catch debug events are enabled for Secure Exception level <n>. |
If EL3 is not implemented and the PE behaves as if SCR_EL3.NS is set to 1, this field is reserved, RES0.
A value of the SE field that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If the SE field is programmed with a reserved value then:
- The PE behaves as if it is programmed with a defined value, other than for a read of EDECCR.
- The value returned for SE by a read of EDECCR is UNKNOWN.
On a Cold reset, this field resets to 0.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Accessing the EDECCR
EDECCR can be accessed through the external debug interface:
Component | Offset | Instance |
---|---|---|
Debug | 0x098 | EDECCR |
This interface is accessible as follows:
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and SoftwareLockStatus() accesses to this register are RO.
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and !SoftwareLockStatus() accesses to this register are RW.
- Otherwise accesses to this register generate an error response.