ERRCRICR1, Critical Error Interrupt Configuration Register 1
The ERRCRICR1 characteristics are:
Purpose
Critical Error Interrupt configuration register.
Configuration
This register is present only when (the Critical Error Interrupt is implemented or the implementation does not use the recommended layout for the ERRIRQCR<n> registers) and interrupt configuration registers are implemented. Otherwise, direct accesses to ERRCRICR1 are RES0.
ERRCRICR1 is implemented only as part of a memory-mapped group of error records.
Attributes
ERRCRICR1 is a 32-bit register.
Field descriptions
The ERRCRICR1 bit assignments are:
When the Critical Error Interrupt is implemented and the implementation uses the recommended layout for the ERRIRQCR<n> registers:31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA |
DATA, bits [31:0]
Payload for the message signaled interrupt.
On an Error recovery reset, this field resets to an architecturally UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
When the implementation does not use the recommended layout for the ERRIRQCR<n> registers:31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IMPLEMENTATION DEFINED
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED, bits [31:0]
IMPLEMENTATION DEFINED.
Accessing the ERRCRICR1
ERRCRICR1 can be accessed through the memory-mapped interfaces:
Component | Offset |
---|---|
RAS | 0xEA8 |
Accesses on this interface are RW.