ERRERICR0, Error Recovery Interrupt Configuration Register 0
The ERRERICR0 characteristics are:
Error Recovery Interrupt configuration register.
This register is present only when (the Error Recovery Interrupt is implemented or the implementation does not use the recommended layout for the ERRIRQCR<n> registers) and interrupt configuration registers are implemented. Otherwise, direct accesses to ERRERICR0 are RES0.
ERRERICR0 is implemented only as part of a memory-mapped group of error records.
ERRERICR0 is a 64-bit register.
The ERRERICR0 bit assignments are:
When the Error Recovery Interrupt is implemented and the implementation uses the recommended layout for the ERRIRQCR<n> registers:
ADDR, bits [55:2]
Message Signaled Interrupt address. (ERRERICR0.ADDR << 2) is the address that the component writes to when signaling the Error Recovery Interrupt. Bits [1:0] of the address are always zero.
The physical address size supported by the component is IMPLEMENTATION DEFINED. Unimplemented high-order physical address bits are RES0.
On an Error recovery reset, this field resets to an architecturally UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
When the implementation does not use the recommended layout for the ERRIRQCR<n> registers:
IMPLEMENTATION DEFINED, bits [63:0]
Accessing the ERRERICR0
ERRERICR0 can be accessed through the memory-mapped interfaces:
Accesses on this interface are RW.