GICC_AEOIR, CPU Interface Aliased End Of Interrupt Register
The GICC_AEOIR characteristics are:
GICC_AEOIR is a 32-bit register.
The GICC_AEOIR bit assignments are:
INTID, bits [23:0]
The INTID of the signaled interrupt.
INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.
When affinity routing is not enabled:
- Bits [23:13] are RES0.
- For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0.
Accessing the GICC_AEOIR
A write to this register must correspond to the most recently acknowledged Group 1 interrupt. If a value other than the last value read from GICC_AIAR is written to this register, the effect is UNPREDICTABLE.
This register is used only when System register access is not enabled. When System register access is enabled:
- For AArch32 implementations, ICC_EOIR1 provides equivalent functionality.
- For AArch64 implementations, ICC_EOIR1_EL1 provides equivalent functionality.
When affinity routing is enabled for a Security state, it is a programming error to use memory-mapped registers to access the GIC.
GICC_AEOIR can be accessed through the memory-mapped interfaces:
|GIC CPU interface||0x0024||GICC_AEOIR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are WO.
- When an access is Secure accesses to this register are WO.
- When an access is Non-secure accesses to this register are WO.