GICC_AIAR, CPU Interface Aliased Interrupt Acknowledge Register
The GICC_AIAR characteristics are:
Provides the INTID of the signaled Group 1 interrupt. A read of this register by the PE acts as an acknowledge for the interrupt.
GICC_AIAR is a 32-bit register.
The GICC_AIAR bit assignments are:
INTID, bits [23:0]
The INTID of the signaled interrupt.
INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.
When affinity routing is not enabled:
- Bits [23:13] are RES0.
- For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0.
Accessing the GICC_AIAR
When affinity routing is enabled for a Security state, it is a programming error to use memory-mapped registers to access the GIC.
GICC_AIAR can be accessed through the memory-mapped interfaces:
|GIC CPU interface||0x0020||GICC_AIAR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RO.
- When an access is Secure accesses to this register are RO.
- When an access is Non-secure accesses to this register are RO.