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GICC_RPR, CPU Interface Running Priority Register

The GICC_RPR characteristics are:


This register indicates the running priority of the CPU interface.


This register is available in all configurations of the GIC. If the GIC implementation supports two Security states this register is Common.


GICC_RPR is a 32-bit register.

Field descriptions

The GICC_RPR bit assignments are:


Bits [31:8]

Reserved, RES0.

Priority, bits [7:0]

The current running priority on the CPU interface. This is the group priority of the current active interrupt.

If there are no active interrupts on the CPU interface, or all active interrupts have undergone a priority drop, the value returned is the Idle priority.

The priority returned is the group priority as if the BPR was set to the minimum value.

Accessing the GICC_RPR

If there is no active interrupt on the CPU interface, the idle priority value is returned.

If the GIC implementation supports two Security states, a Non-secure read of the Priority field returns:

  • 0x00 if the field value is less than 0x80.
  • The Non-secure view of the Priority value if the field value is 0x80 or more.

For more information, see 'Interrupt prioritization' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).


Software cannot determine the number of implemented priority bits from this register.

GICC_RPR can be accessed through the memory-mapped interfaces:

GIC CPU interface0x0014GICC_RPR

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0 accesses to this register are RO.
  • When an access is Secure accesses to this register are RO.
  • When an access is Non-secure accesses to this register are RO.