GICD_ICPENDR<n>E, Interrupt Clear-Pending Registers (extended SPI range), n = 0 - 31
The GICD_ICPENDR<n>E characteristics are:
Removes the pending state to the corresponding SPI in the extended SPI range.
This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICD_ICPENDR<n>E are RES0.
When GICD_TYPER.ESPI==0, these registers are RES0.
GICD_ICPENDR<n>E is a 32-bit register.
The GICD_ICPENDR<n>E bit assignments are:
|Clear_pending_bit<x>, bit [x], for x = 0 to 31|
Clear_pending_bit<x>, bit [x], for x = 0 to 31
For the extended PPIs, removes the pending state to interrupt number x. Reads and writes have the following behavior:
If read, indicates that the corresponding interrupt is not pending.
If written, has no effect.
If read, indicates that the corresponding interrupt is pending, or active and pending.
If written, changes the state of the corresponding interrupt from pending to inactive, or from active and pending to active.
This has no effect in the following cases:
This field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
- The corresponding GICD_ICPENDR<n>E number, n, is given by n = (m-4096) DIV 32.
- The offset of the required GICD_ICPENDR<n>E is (0x1800 + (4*n)).
- The bit number of the required group modifier bit in this register is (m-4096) MOD 32.
Accessing the GICD_ICPENDR<n>E
When affinity routing is not enabled for the Security state of an interrupt in GICD_ICPENDR<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
GICD_ICPENDR<n>E can be accessed through the memory-mapped interfaces:
|GIC Distributor||0x1800 + (4 * n)||GICD_ICPENDR<n>E|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.