GICD_IGRPMODR<n>, Interrupt Group Modifier Registers, n = 0 - 31
The GICD_IGRPMODR<n> characteristics are:
- Secure Group 0.
- Non-secure Group 1.
- Secure Group 1.
When GICD_CTLR.DS==0, these registers are Secure.
GICD_IGRPMODR<n> is a 32-bit register.
The GICD_IGRPMODR<n> bit assignments are:
|Group_modifier_bit<x>, bit [x], for x = 0 to 31|
Group_modifier_bit<x>, bit [x], for x = 0 to 31
Group modifier bit. When affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICD_IGROUPR<n> to form a 2-bit field that defines an interrupt group:
|Group modifier bit||Group status bit||Definition||Short name|
|0b0||0b0||Secure Group 0||G0S|
|0b0||0b1||Non-secure Group 1||G1NS|
|0b1||0b0||Secure Group 1||G1S|
|0b1||0b1||Reserved, treated as Non-secure Group 1||-|
This field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
- The corresponding GICD_IGRPMODR<n> number, n, is given by n = m DIV 32.
- The offset of the required GICD_IGRPMODR is (0x080 + (4*n)).
- The bit number of the required group modifier bit in this register is m MOD 32.
See GICD_IGROUPR<n> for information about the GICD_IGRPMODR0 reset value.
Accessing the GICD_IGRPMODR<n>
When affinity routing is enabled for Secure state, GICD_IGRPMODR0 is RES0 and equivalent functionality is proved by GICR_IGRPMODR0.
When GICD_CTLR.DS==0, the register is RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.
GICD_IGRPMODR<n> can be accessed through the memory-mapped interfaces:
|GIC Distributor||0x0D00 + (4 * n)||GICD_IGRPMODR<n>|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.