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GICD_ISPENDR<n>, Interrupt Set-Pending Registers, n = 0 - 31

The GICD_ISPENDR<n> characteristics are:

Purpose

Adds the pending state to the corresponding interrupt.

Configuration

These registers are available in all GIC configurations. If GICD_CTLR.DS==0, these registers are Common.

The number of implemented GICD_ISPENDR<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.

GICD_ISPENDR0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.

Accessing GICD_ISPENDR0 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:

  • Register is RAZ/WI.
  • An UNKNOWN banked copy of the register is accessed.

Attributes

GICD_ISPENDR<n> is a 32-bit register.

Field descriptions

The GICD_ISPENDR<n> bit assignments are:

313029282726252423222120191817161514131211109876543210
Set_pending_bit<x>, bit [x], for x = 0 to 31

Set_pending_bit<x>, bit [x], for x = 0 to 31

For SPIs and PPIs, adds the pending state to interrupt number 32n + x. Reads and writes have the following behavior:

Set_pending_bit<x>Meaning
0b0

If read, indicates that the corresponding interrupt is not pending on any PE.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is pending, or active and pending:

  • On this PE if the interrupt is an SGI or PPI.
  • On at least one PE if the interrupt is an SPI.

If written, changes the state of the corresponding interrupt from inactive to pending, or from active to active and pending. This has no effect in the following cases:

  • If the interrupt is an SGI. The pending state of an SGI can be set using GICD_SPENDSGIR<n>.
  • If the interrupt is not inactive and is not active.
  • If the interrupt is already pending because of a write to GICD_ISPENDR<n>.
  • If the interrupt is already pending because the corresponding interrupt signal is asserted. In this case, the interrupt remains pending if the interrupt signal is deasserted.

This field resets to 0.

Accessing the GICD_ISPENDR<n>

Set-pending bits for SGIs are read-only and ignore writes. The Set-pending bits for SGIs are provided as GICD_SPENDSGIR<n>.

When affinity routing is enabled for the Security state of an interrupt:

  • Bits corresponding to SGIs and PPIs are RAZ/WI, and equivalent functionality for SGIs and PPIs is provided by GICR_ISPENDR0.
  • Bits corresponding to Group 0 and Group 1 Secure interrupts can only be set by Secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

If GICD_CTLR.DS==0, unless the GICD_NSACR<n> registers permit Non-secure software to control Group 0 and Secure Group 1 interrupts, any bits that correspond to Group 0 or Secure Group 1 interrupts are accessible only by Secure accesses and are RAZ/WI to Non-secure accesses.

GICD_ISPENDR<n> can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
GIC Distributor0x0200 + (4 * n)GICD_ISPENDR<n>

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0 accesses to this register are RW.
  • When an access is Secure accesses to this register are RW.
  • When an access is Non-secure accesses to this register are RW.


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