GICR_ICFGR0, Interrupt Configuration Register 0
The GICR_ICFGR0 characteristics are:
Determines whether the corresponding SGI is edge-triggered or level-sensitive.
A copy of this register is provided for each Redistributor.
GICR_ICFGR0 is a 32-bit register.
The GICR_ICFGR0 bit assignments are:
|Int_config<x>, bits [2x+1:2x], for x = 0 to 15|
Int_config<x>, bits [2x+1:2x], for x = 0 to 15
Indicates whether the interrupt with ID 16n + x is level-sensitive or edge-triggered.
Int_config (bit [2x]) is RES0.
Possible values of Int_config (bit [2x+1]) are:
Corresponding interrupt is level-sensitive.
Corresponding interrupt is edge-triggered.
For SGIs, Int_config is RAO/WI.
A read of this bit always returns the correct value to indicate the interrupt triggering method.
This field resets to an architecturally UNKNOWN value.
Accessing the GICR_ICFGR0
This register is used when affinity routing is enabled.
When affinity routing is disabled for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case. Equivalent functionality is provided by GICD_ICFGR<n> with n=0.
When GICD_CTLR.DS==0, a register bit that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses.
GICR_ICFGR0 can be accessed through the memory-mapped interfaces:
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.