GICR_ISENABLER<n>E, Interrupt Set-Enable Registers, n = 1 - 2
The GICR_ISENABLER<n>E characteristics are:
Purpose
Enables forwarding of the corresponding PPI to the CPU interfaces.
Configuration
This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICR_ISENABLER<n>E are RES0.
A copy of this register is provided for each Redistributor.
Attributes
GICR_ISENABLER<n>E is a 32-bit register.
Field descriptions
The GICR_ISENABLER<n>E bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Set_enable_bit<x>, bit [x], for x = 0 to 31 | |||||||||||||||||||||||||||||||
Set_enable_bit<x>, bit [x], for x = 0 to 31
For the extended PPI range, controls the forwarding of interrupt number x to the CPU interface. Reads and writes have the following behavior:
| Set_enable_bit<x> | Meaning |
|---|---|
| 0b0 |
If read, indicates that forwarding of the corresponding interrupt is disabled. If written, has no effect. |
| 0b1 |
If read, indicates that forwarding of the corresponding interrupt is enabled. If written, enables forwarding of the corresponding interrupt. After a write of 1 to this bit, a subsequent read of this bit returns 1. |
This field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
- The corresponding GICR_ISENABLER<n>E number, n, is given by n = (m-1024) DIV 32.
- The offset of the required GICR_ISENABLER<n>E is (0x100 + (4*n)).
- The bit number of the required group modifier bit in this register is (m-1024) MOD 32.
Accessing the GICR_ISENABLER<n>E
When affinity routing is not enabled for the Security state of an interrupt in GICR_ISENABLER<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
GICR_ISENABLER<n>E can be accessed through the memory-mapped interfaces:
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Redistributor | SGI_base | 0x0100 + (4 * n) | GICR_ISENABLER<n>E |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.