GICR_ISPENDR0, Interrupt Set-Pending Register 0
The GICR_ISPENDR0 characteristics are:
Adds the pending state to the corresponding SGI or PPI.
A copy of this register is provided for each Redistributor.
GICR_ISPENDR0 is a 32-bit register.
The GICR_ISPENDR0 bit assignments are:
|Set_pending_bit<x>, bit [x], for x = 0 to 31|
Set_pending_bit<x>, bit [x], for x = 0 to 31
For PPIs and SGIs, adds the pending state to interrupt number x. Reads and writes have the following behavior:
If read, indicates that the corresponding interrupt is not pending on this PE.
If written, has no effect.
If read, indicates that the corresponding interrupt is pending, or active and pending on this PE.
If written, changes the state of the corresponding interrupt from inactive to pending, or from active to active and pending. This has no effect in the following cases:
This field resets to an architecturally UNKNOWN value.
Accessing the GICR_ISPENDR0
When affinity routing is not enabled for the Security state of an interrupt in GICR_ISPENDR0, the corresponding bit is RAZ/WI and equivalent functionality is provided by GICD_ISPENDR<n> with n=0.
This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by GICD_ISPENDR<n>.
When GICD_CTLR.DS == 0, bits corresponding to Secure SGIs and PPIs are RAZ/WI to Non-secure accesses.
GICR_ISPENDR0 can be accessed through the memory-mapped interfaces:
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.