GICR_SETLPIR, Set LPI Pending Register
The GICR_SETLPIR characteristics are:
Purpose
Generates an LPI by setting the pending state of the specified LPI.
Configuration
This register is present only when FEAT_GICv4p1 is implemented. Otherwise, direct accesses to GICR_SETLPIR are RES0.
A copy of this register is provided for each Redistributor.
Attributes
GICR_SETLPIR is a 64-bit register.
Field descriptions
The GICR_SETLPIR bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| pINTID | |||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:32]
Reserved, RES0.
pINTID, bits [31:0]
The INTID of the physical LPI to be generated.
The size of this field is IMPLEMENTATION DEFINED, and is specified by the GICD_TYPER.IDbits field. Unimplemented bits are RES0.
Accessing the GICR_SETLPIR
When written with a 32-bit write the data is zero-extended to 64 bits.
This register is mandatory in an implementation that supports LPIs and does not include an ITS. The functionality is IMPLEMENTATION DEFINED in an implementation that does include an ITS.
Writes to this register have no effect if either:
- The pINTID field corresponds to an LPI that is already pending.
- The pINTID field corresponds to an unimplemented LPI.
- GICR_CTLR.EnableLPIs == 0.
GICR_SETLPIR can be accessed through the memory-mapped interfaces:
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Redistributor | RD_base | 0x0040 | GICR_SETLPIR |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are WO.
- When an access is Secure accesses to this register are WO.
- When an access is Non-secure accesses to this register are WO.