GICR_STATUSR, Error Reporting Status Register
The GICR_STATUSR characteristics are:
Purpose
Provides software with a mechanism to detect:
- Accesses to reserved locations.
- Writes to read-only locations.
- Reads of write-only locations.
Configuration
A copy of this register is provided for each Redistributor.
If the GIC implementation supports two Security states this register is Banked to provide Secure and Non-secure copies.
Attributes
GICR_STATUSR is a 32-bit register.
Field descriptions
The GICR_STATUSR bit assignments are:
Bits [31:4]
Reserved, RES0.
WROD, bit [3]
Write to an RO location.
WROD | Meaning |
---|---|
0b0 |
Normal operation. |
0b1 |
A write to an RO location has been detected. |
When a violation is detected, software must write 1 to this register to reset it.
RWOD, bit [2]
Read of a WO location.
RWOD | Meaning |
---|---|
0b0 |
Normal operation. |
0b1 |
A read of a WO location has been detected. |
When a violation is detected, software must write 1 to this register to reset it.
WRD, bit [1]
Write to a reserved location.
WRD | Meaning |
---|---|
0b0 |
Normal operation. |
0b1 |
A write to a reserved location has been detected. |
When a violation is detected, software must write 1 to this register to reset it.
RRD, bit [0]
Read of a reserved location.
RRD | Meaning |
---|---|
0b0 |
Normal operation. |
0b1 |
A read of a reserved location has been detected. |
When a violation is detected, software must write 1 to this register to reset it.
Accessing the GICR_STATUSR
This is an optional register. If the register is not implemented, the location is RAZ/WI.
GICR_STATUSR can be accessed through the memory-mapped interfaces:
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | RD_base | 0x0010 | GICR_STATUSR (S) |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | RD_base | 0x0010 | GICR_STATUSR (NS) |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.