GICR_SYNCR, Redistributor Synchronize Register
The GICR_SYNCR characteristics are:
Purpose
Indicates completion of register based invalidate operations.
Configuration
A copy of this register is provided for each Redistributor.
Attributes
GICR_SYNCR is a 32-bit register.
Field descriptions
The GICR_SYNCR bit assignments are:
Bits [31:1]
Reserved, RES0.
Busy, bit [0]
Indicates completion of invalidation operations
| Busy | Meaning |
|---|---|
| 0b0 |
No operations are in progress. |
| 0b1 |
A write is in progress to one or more of the following registers:
|
This field tracks operations initiated on the same Redistributor.
Accessing the GICR_SYNCR
When this register is accessed, it is optional that an implementation might wait until all operations are complete before returning a value, in which case GICR_SYNCR.Busy is always 0.
This register is mandatory in an implementation that supports LPIs and does not include an ITS. The functionality is IMPLEMENTATION DEFINED in an implementation that does include an ITS.
GICR_SYNCR can be accessed through the memory-mapped interfaces:
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Redistributor | RD_base | 0x00C0 | GICR_SYNCR |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RO.
- When an access is Secure accesses to this register are RO.
- When an access is Non-secure accesses to this register are RO.