GICR_VSGIR, Redistributor virtual SGI pending state request register
The GICR_VSGIR characteristics are:
Requests the pending state of virtual SGIs for a specified vPE.
This register is present only when FEAT_GICv4p1 is implemented. Otherwise, direct accesses to GICR_VSGIR are RES0.
A copy of this register is provided for each Redistributor.
GICR_VSGIR is a 32-bit register.
The GICR_VSGIR bit assignments are:
vPEID, bits [15:0]
ID of target vPE
Writing this field is CONSTRAINED UNPREDICTABLE when GICR_VSGIPENDR.Busy == 1, with either the write ignored or a new query started.
Writing a value greater than the configured vPEID width behaviur is CONSTRAINED UNPREDICTABLE:
GICR_VPENDBASER.vPEID is treated as having an UNKNOWN valid value for all purposes other than a direct read of the register.
GICR_VPENDBASER.Valid is treated as being set to 0 for all purposes other than a direct read of the register.
Accessing the GICR_VSGIR
64-bit access only.
GICR_VSGIR can be accessed through the memory-mapped interfaces:
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are WO.
- When an access is Secure accesses to this register are WO.
- When an access is Non-secure accesses to this register are WO.