GICV_AEOIR, Virtual Machine Aliased End Of Interrupt Register
The GICV_AEOIR characteristics are:
A write to this register performs a priority drop for the specified Group 1 virtual interrupt and, if GICV_CTLR.EOImode == 0, also deactivates the interrupt.
This register is available when the GIC implementation supports interrupt virtualization.
GICV_AEOIR is a 32-bit register.
The GICV_AEOIR bit assignments are:
INTID, bits [24:0]
The INTID of the signaled interrupt.
INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.
When affinity routing is not enabled:
- Bits [23:13] are RES0.
- For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0.
A successful EOI request means that:
- The highest priority bit in GICH_APR<n> is cleared, causing the running priority to drop.
- If the appropriate GICV_CTLR.EOImode bit == 0, the interrupt is deactivated in the corresponding List register. If the INTID corresponds to a hardware interrupt, the interrupt is also deactivated in the Distributor.
Only Group 1 interrupts can target the hypervisor, and therefore only Group 1 interrupts are deactivated in the Distributor.
A write to this register is UNPREDICTABLE if the INTID corresponds to a Group 0 interrupt. In addition, the following GICv2 UNPREDICTABLE cases require specific actions:
- If highest active priority is Group 0 and the identified interrupt is in the List Registers and it matches the highest active priority. When EL2 is using System registers and ICH_VTR_EL2.SEIS is 1, an IMPLEMENTATION DEFINED SEI might be generated, otherwise GICv3 implementations must ignore such writes.
- If the identified interrupt is in the List Registers, and the HW bit is 1, and the interrupt to be deactivated is an SGI (that is, the value of Physical_ID is between 0 and 15). GICv3 implementations must perform the deactivate operation. This means that a GICv3 implementation in legacy operation must ensure only a single SGI is active for a PE.
- If the identified interrupt is in the List Registers, and the HW bit is 1, and the corresponding pINTID field value is between 1020 and 1023, indicating a special purpose INTID. GICv3 implementations must not perform a deactivate operation but must still change the state of the List register as appropriate. When EL2 is using System registers and ICH_VTR_EL2.SEIS is 1, an implementation might generate a system error.
Accessing the GICV_AEOIR
This register is used only when System register access is not enabled. When System register access is enabled:
- For AArch32 implementations, ICC_EOIR1 provides equivalent functionality.
- For AArch64 implementations, ICC_EOIR1_EL1 provides equivalent functionality.
This register is used for Group 1 interrupts only. GICV_EOIR provides equivalent functionality for Group 0 interrupts.
When affinity routing is enabled, it is a programming error to use memory-mapped registers to access the GIC.
GICV_AEOIR can be accessed through the memory-mapped interfaces:
|GIC Virtual CPU interface||0x0024||GICV_AEOIR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are WO.
- When an access is Secure accesses to this register are WO.
- When an access is Non-secure accesses to this register are WO.