GICV_AHPPIR, Virtual Machine Aliased Highest Priority Pending Interrupt Register
The GICV_AHPPIR characteristics are:
Provides the INTID of the highest priority pending Group 1 virtual interrupt in the List registers.
This register corresponds to the physical CPU interface register GICC_AHPPIR.
This register is available when the GIC implementation supports interrupt virtualization.
GICV_AHPPIR is a 32-bit register.
The GICV_AHPPIR bit assignments are:
INTID, bits [24:0]
The INTID of the signaled interrupt.
INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.
When affinity routing is not enabled:
- Bits [23:13] are RES0.
- For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0.
A read of this register returns the spurious INTID 1023 if any of the following are true:
- There are no pending interrupts of sufficiently high priority value to be signaled to the PE.
- The highest priority pending interrupt is in Group 0.
Accessing the GICV_AHPPIR
This register is used only when System register access is not enabled. When System register access is enabled:
- For AArch32 implementations, ICC_HPPIR1 provides equivalent functionality.
- For AArch64 implementations, ICC_HPPIR1_EL1 provides equivalent functionality.
This register is used for Group 1 interrupts only. GICV_HPPIR provides equivalent functionality for Group 0 interrupts.
The register does not return the INTID of an interrupt that is active and pending.
When affinity routing is enabled, it is a programming error to use memory-mapped registers to access the GIC.
GICV_AHPPIR can be accessed through the memory-mapped interfaces:
|GIC Virtual CPU interface||0x0028||GICV_AHPPIR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RO.
- When an access is Secure accesses to this register are RO.
- When an access is Non-secure accesses to this register are RO.