GICV_BPR, Virtual Machine Binary Point Register
The GICV_BPR characteristics are:
Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 0 interrupt preemption.
This register corresponds to GICC_BPR in the physical CPU interface.
GICH_LR<n>.Group determines whether a virtual interrupt is Group 0 or Group 1.
This register is available when the GIC implementation supports interrupt virtualization.
When GICV_CTLR.CBPR == 1, this register determines interrupt preemption for both Group 0 and Group 1 interrupts.
GICV_BPR is a 32-bit register.
The GICV_BPR bit assignments are:
Binary_Point, bits [2:0]
Controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field.
For information about how this field determines the interrupt priority bits assigned to the group priority field, see 'ICC_BPR0_EL1 Binary Point for Group 1 interrupts when CBPR == 1, or for Group 0 interrupts' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
This field resets to an architecturally UNKNOWN value.
The Binary_Point field of this register is aliased to GICH_VMCR.VBPR0.
Accessing the GICV_BPR
This register is used only when System register access is not enabled. When System register access is enabled:
- For AArch32 implementations, ICC_BPR0 provides equivalent functionality.
- For AArch64 implementations, ICC_BPR0_EL1 provides equivalent functionality.
GICV_BPR can be accessed through the memory-mapped interfaces:
|GIC Virtual CPU interface||0x0008||GICV_BPR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RW.
- When an access is Secure accesses to this register are RW.
- When an access is Non-secure accesses to this register are RW.