GICV_IIDR, Virtual Machine CPU Interface Identification Register
The GICV_IIDR characteristics are:
Provides information about the implementer and revision of the virtual CPU interface.
This register is available in all configurations of the GIC. If the GIC implementation supports two Security states this register is Common.
GICV_IIDR is a 32-bit register.
The GICV_IIDR bit assignments are:
ProductID, bits [31:20]
An IMPLEMENTATION DEFINED product identifier.
Architecture_version, bits [19:16]
The version of the GIC architecture that is implemented.
GICv3 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1.
GICv4 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1.
Other values are reserved.
Revision, bits [15:12]
An IMPLEMENTATION DEFINED revision number for the CPU interface.
Implementer, bits [11:0]
Contains the JEP106 code of the company that implemented the CPU interface.
- Bits [11:8] are the JEP106 continuation code of the implementer. For an Arm implementation, this field is 0x4.
- Bit  is always 0.
- Bits [6:0] are the JEP106 identity code of the implementer. For an Arm implementation, bits [7:0] are therefore 0x3B.
Accessing the GICV_IIDR
GICV_IIDR can be accessed through the memory-mapped interfaces:
|GIC Virtual CPU interface||0x00FC||GICV_IIDR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RO.
- When an access is Secure accesses to this register are RO.
- When an access is Non-secure accesses to this register are RO.