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GITS_TRANSLATER, ITS Translation Register

The GITS_TRANSLATER characteristics are:


Written by a requesting Device to signal an interrupt for translation by the ITS.


This register is at the same offset as GICD_SETSPI_NSR in the Distributor, and is at the same offset as GICR_SETLPIR in the Redistributor.


GITS_TRANSLATER is a 32-bit register.

Field descriptions

The GITS_TRANSLATER bit assignments are:


EventID, bits [31:0]

An identifier corresponding to the interrupt to be translated.


The size of the EventID is DeviceID specific, and set when the DeviceID is mapped to an ITT (using MAPD).

The number of EventID bits implemented is reported by GITS_TYPER.ID_bits. If a write specifies non-zero identifiers bits outside this range behavior is a CONSTRAINED UNPREDICTABLE choice between:

  • Non-zero identifier bits outside the supported range are ignored.
  • The write is ignored.

The DeviceID presented to an ITS is used to index a device table. The device table maps the DeviceID to an interrupt translation table for that device.


16-bit access to bits [15:0] of this register must be supported. When this register is written by a 16-bit transaction, bits [31:16] are written as zero.

Implementations must ensure that:

  • A unique DeviceID is provided for each requesting device, and the DeviceID is presented to the ITS when a write to this register occurs in a manner that cannot be spoofed by any agent capable of performing writes.
  • The DeviceID presented corresponds to the DeviceID field in the ITS commands.

Writes to this register are ignored if any of the following are true:

  • GITS_CTLR.Enabled == 0.
  • The presented DeviceID is not mapped to an Interrupt Translation Table.
  • The DeviceID is larger than the supported size.
  • The DeviceID is mapped to an Interrupt Translation Table, but the EventID is outside the range specified by MAPD.
  • The EventID is mapped to an Interrupt Translation Table and the EventID is within the range specified by MAPD, but the EventID is unmapped.

Translation requests that result from writes to this register are subject to certain ordering rules. For more information, see 'Ordering of translations with the output to ITS commands' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).

GITS_TRANSLATER can be accessed through the memory-mapped interfaces:

GIC ITS translation0x0040GITS_TRANSLATER

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0 accesses to this register are WO.
  • When an access is Secure accesses to this register are WO.
  • When an access is Non-secure accesses to this register are WO.