MPAMCFG_CPBM<n>, MPAM Cache Portion Bitmap Partition Configuration Register, n = 0 - 1023
The MPAMCFG_CPBM<n> characteristics are:
Purpose
The MPAMCFG_CPBM<n> register array gives access to the cache portion bitmap. Each register in the array is a read-write register that configures the cache portions numbered from 32n to 32n + 31 that a PARTID is allowed to allocate.
After setting MPAMCFG_PART_SEL with a PARTID, software writes to the MPAMCFG_CPBM<n> register to configure which cache portions the PARTID is allowed to allocate.
The MPAMCFG_CPBM<n> register that contains the bitmap bit corresponding to cache portion p has n equal to p >> 5. The field, P<x>, of that MPAMCFG_CPBM<n> register that contain the bitmap bit corresponding to cache portion p has x equal to p & 0x1F.
MPAMCFG_CPBM<n>_s controls cache portions for the Secure PARTID selected by the Secure instance of MPAMCFG_PART_SEL. MPAMCFG_CPBM<n>_ns controls the cache portions for the Non-secure PARTID selected by the Non-secure instance of MPAMCFG_PART_SEL.
If MPAMF_IDR.HAS_RIS is 1, the control settings accessed are those of the resource instance currently selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.
Configuration
The power domain of MPAMCFG_CPBM<n> is IMPLEMENTATION DEFINED.
This register is present only when MPAMF_IDR.HAS_CPOR_PART == 1. Otherwise, direct accesses to MPAMCFG_CPBM<n> are RES0.
Attributes
MPAMCFG_CPBM<n> is a 32-bit register.
Field descriptions
The MPAMCFG_CPBM<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P31 | P30 | P29 | P28 | P27 | P26 | P25 | P24 | P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
P<x>, bit [x], for x = 0 to 31
Portion allocation control bit. Each cache portion allocation control bit, MPAMCFG_CPBM<n>.P<x>, grants permission to the PARTID selected by MPAMCFG_PART_SEL to allocate cache lines within cache portion 32n + x.
P<x> | Meaning |
---|---|
0b0 |
The PARTID is not permitted to allocate into cache portion 32n + x. |
0b1 |
The PARTID is permitted to allocate within cache portion 32n + x. |
The number of bits in the cache portion partitioning bit map of this component is given in MPAMF_CPOR_IDR.CPBM_WD. CPBM_WD contains a value from 1 to 215, inclusive. Values of CPBM_WD greater than 32 require an array of 32-bit MPAMCFG_CPBM<n> registers to access the cache portion bitmap, up to 1024 registers.
Bits MPAMCFG_CPBM<n>.P<x>, where 32n + x is greater than CPBM_WD, are not required to be implemented.
Accessing the MPAMCFG_CPBM<n>
This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.
MPAMCFG_CPBM<n>_s must be accessible from the Secure MPAM feature page. MPAMCFG_CPBM<n>_ns must be accessible from the Non-secure MPAM feature page.
MPAMCFG_CPBM<n>_s and MPAMCFG_CPBM<n>_ns must be separate registers. The Secure instance (MPAMCFG_CPBM<n>_s) accesses the cache portion bitmap used for Secure PARTIDs, and the Non-secure instance (MPAMCFG_CPBM<n>_ns) accesses the cache portion bitmap used for Non-secure PARTIDs.
When RIS is implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the cache resource instance selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.
When RIS is not implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.
When PARTID narrowing is implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the internal PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 1.
When PARTID narrowing is not implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the request PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 0.
MPAMCFG_CPBM<n> can be accessed through the memory-mapped interfaces:
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x1000 + (4 * n) | MPAMCFG_CPBM<n>_s |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x1000 + (4 * n) | MPAMCFG_CPBM<n>_ns |
Accesses on this interface are RW.