MPAMF_AIDR, MPAM Architecture Identification Register
The MPAMF_AIDR characteristics are:
Purpose
Identifies the version of the MPAM architecture that this MSC implements.
Note: The following values are defined for bits [7:0]:
-
0x01 == MPAM architecture v0.1
-
0x10 == MPAM architecture v1.0
-
0x11 == MPAM architecture v1.1
Configuration
The power domain of MPAMF_AIDR is IMPLEMENTATION DEFINED.
Attributes
MPAMF_AIDR is a 32-bit register.
Field descriptions
The MPAMF_AIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | ArchMajorRev | ArchMinorRev |
Bits [31:8]
Reserved, RES0.
ArchMajorRev, bits [7:4]
Major revision of the MPAM architecture implemented by the MSC.
This table shows the only valid combinations of MPAM version numbers in an MSC. FORCE_NS functionality is only available in MPAM v0.1.
ArchMajorRev | ArchMinorRev | MPAMv | Available |
---|---|---|---|
0 | 0 | None. | |
0 | 1 | v0.1 | MPAMv1.0 + MPAMv1.1 + FORCE_NS |
1 | 0 | v1.0 | MPAMv1.0 |
1 | 1 | v1.1 | MPAMv1.0 + MPAMv1.1 - FORCE_NS |
ArchMinorRev, bits [3:0]
Minor revision of the MPAM architecture implemented by the MSC.
See the table in the description of the ArchMajorRev field in this register.
Accessing the MPAMF_AIDR
This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.
MPAMF_AIDR is read-only.
MPAMF_AIDR must be readable from the Non-secure and Secure MPAM feature pages.
MPAMF_AIDR must have the same contents in the Secure and Non-secure MPAM feature pages.
MPAMF_AIDR can be accessed through the memory-mapped interfaces:
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x0020 | MPAMF_AIDR |
Accesses on this interface are RO.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x0020 | MPAMF_AIDR |
Accesses on this interface are RO.