PMCCFILTR_EL0, Performance Monitors Cycle Counter Filter Register
The PMCCFILTR_EL0 characteristics are:
Purpose
Determines the modes in which the Cycle Counter, PMCCNTR_EL0, increments.
Configuration
External register PMCCFILTR_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMCCFILTR_EL0[31:0] .
External register PMCCFILTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCCFILTR[31:0] .
PMCCFILTR_EL0 is in the Core power domain.
On a Warm or Cold reset, RW fields in this register reset:
-
To architecturally UNKNOWN values if the reset is to an Exception level that is using AArch64.
-
To 0 if the reset is to an Exception level that is using AArch32.
The register is not affected by an External debug reset.
Attributes
PMCCFILTR_EL0 is a 32-bit register.
Field descriptions
The PMCCFILTR_EL0 bit assignments are:
P, bit [31]
Privileged filtering bit. Controls counting in EL1.
If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the PMCCFILTR_EL0.NSK bit.
| P | Meaning |
|---|---|
| 0b0 |
Count cycles in EL1. |
| 0b1 |
Do not count cycles in EL1. |
U, bit [30]
User filtering bit. Controls counting in EL0.
If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the PMCCFILTR_EL0.NSU bit.
| U | Meaning |
|---|---|
| 0b0 |
Count cycles in EL0. |
| 0b1 |
Do not count cycles in EL0. |
NSK, bit [29]
When EL3 is implemented:
When EL3 is implemented:
Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.P bit, cycles in Non-secure EL1 are counted.
Otherwise, cycles in Non-secure EL1 are not counted.
Otherwise:
Otherwise:
Reserved, RES0.
NSU, bit [28]
When EL3 is implemented:
When EL3 is implemented:
Non-secure EL0 (Unprivileged) filtering bit. Controls counting in Non-secure EL0.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.U bit, cycles in Non-secure EL0 are counted.
Otherwise, cycles in Non-secure EL0 are not counted.
Otherwise:
Otherwise:
Reserved, RES0.
NSH, bit [27]
When EL2 is implemented:
When EL2 is implemented:
EL2 (Hypervisor) filtering bit. Controls counting in EL2.
If Secure EL2 is implemented, and EL3 is implemented, counting in Secure EL2 is further controlled by the PMCCFILTR_EL0.SH bit.
| NSH | Meaning |
|---|---|
| 0b0 |
Do not count cycles in EL2. |
| 0b1 |
Count cycles in EL2. |
Otherwise:
Otherwise:
Reserved, RES0.
M, bit [26]
When EL3 is implemented:
When EL3 is implemented:
Secure EL3 filtering bit.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.P bit, cycles in Secure EL3 are counted.
Otherwise, cycles in Secure EL3 are not counted.
Most applications can ignore this field and set its value to 0.
This field is not visible in the AArch32 PMCCFILTR System register.
Otherwise:
Otherwise:
Reserved, RES0.
Bit [25]
Reserved, RES0.
SH, bit [24]
When FEAT_SEL2 is implemented:
When FEAT_SEL2 is implemented:
Secure EL2 filtering.
If the value of this bit is not equal to the value of the PMCCFILTR_EL0.NSH bit, cycles in Secure EL2 are counted.
Otherwise, cycles in Secure EL2 are not counted.
If Secure EL2 is disabled, this field is RES0.
This field is not visible in the AArch32 PMCCFILTR System register.
Otherwise:
Otherwise:
Reserved, RES0.
Bits [23:0]
Reserved, RES0.
Accessing the PMCCFILTR_EL0
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
PMCCFILTR_EL0 can be accessed through the external debug interface:
| Component | Offset | Instance |
|---|---|---|
| PMU | 0x47C | PMCCFILTR_EL0 |
This interface is accessible as follows:
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus(), AllowExternalPMUAccess() and SoftwareLockStatus() accesses to this register are RO.
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus(), AllowExternalPMUAccess() and !SoftwareLockStatus() accesses to this register are RW.
- Otherwise accesses to this register generate an error response.