PMCID1SR, CONTEXTIDR_EL1 Sample Register

The PMCID1SR characteristics are:

Purpose

Contains the sampled value of CONTEXTIDR_EL1, captured on reading PMPCSR[31:0].

Configuration

PMCID1SR is in the Core power domain.

This register is present only when FEAT_PCSRv8p2 is implemented. Otherwise, direct accesses to PMCID1SR are RES0.

Attributes

PMCID1SR is a 32-bit register.

Field descriptions

The PMCID1SR bit assignments are:

CONTEXTIDR_EL1, bits [31:0]

Context ID. The value of CONTEXTIDR that is associated with the most recent PMPCSR sample. When the most recent PMPCSR sample was generated:

• If EL1 is using AArch64, then the Context ID is sampled from CONTEXTIDR_EL1.
• If EL1 is using AArch32, then the Context ID is sampled from CONTEXTIDR.
• If EL3 is implemented and is using AArch32, then CONTEXTIDR is a banked register and PMCID1SR samples the current banked copy of CONTEXTIDR for the Security state that is associated with the most recent PMPCSR sample.

Because the value written to PMCID1SR is an indirect read of CONTEXTIDR, it is CONSTRAINED UNPREDICTABLE whether PMCID1SR is set to the original or new value if PMPCSR samples:

• An instruction that writes to CONTEXTIDR.
• The next Context synchronization event.
• Any instruction executed between these two instructions.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

On an External debug reset, the value of this field is unchanged.

On a Warm reset, the value of this field is unchanged.

Accessing the PMCID1SR

IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'.

PMCID1SR can be accessed through the external debug interface:

This interface is accessible as follows:

• When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus() accesses to this register are RO.
• Otherwise accesses to this register generate an error response.

This interface is accessible as follows:

• When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus() accesses to this register are RO.
• Otherwise accesses to this register generate an error response.