PMCIDR1, Performance Monitors Component Identification Register 1
The PMCIDR1 characteristics are:
Provides information to identify a Performance Monitor component.
For more information, see 'About the Component Identification scheme'.
Implementation of this register is OPTIONAL.
If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
PMCIDR1 is a 32-bit register.
The PMCIDR1 bit assignments are:
CLASS, bits [7:4]
Other values are defined by the CoreSight Architecture.
This field reads as 0x9.
PRMBL_1, bits [3:0]
Reads as 0b0000.
Accessing the PMCIDR1
PMCIDR1 can be accessed through the external debug interface:
This interface is accessible as follows:
- When FEAT_DoPD is not implemented or IsCorePowered() accesses to this register are RO.
- Otherwise accesses to this register generate an error response.