PMCR_EL0, Performance Monitors Control Register
The PMCR_EL0 characteristics are:
Purpose
Provides details of the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters.
Configuration
External register PMCR_EL0 bits [7:0] are architecturally mapped to AArch32 System register PMCR[7:0] .
External register PMCR_EL0 bits [7:0] are architecturally mapped to AArch64 System register PMCR_EL0[7:0] .
PMCR_EL0 is in the Core power domain.
This register is only partially mapped to the internal PMCR System register. An external agent must use other means to discover the information held in PMCR[31:11], such as accessing PMCFGR and the ID registers.
Attributes
PMCR_EL0 is a 32-bit register.
Field descriptions
The PMCR_EL0 bit assignments are:
Bits [31:11]
Reserved, RAZ/WI.
Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register.
Bits [10:8]
Reserved, RES0.
LP, bit [7]
When FEAT_PMUv3p5 is implemented:
When FEAT_PMUv3p5 is implemented:
Long event counter enable. Determines when unsigned overflow is recorded by a counter overflow bit.
| LP | Meaning |
|---|---|
| 0b0 |
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[31:0]. |
| 0b1 |
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[63:0]. |
If EL2 is implemented and MDCR_EL2.HPMN is less than PMCR_EL0.N, this bit does not affect the operation of event counters in the range [MDCR_EL2.HPMN:(PMCR_EL0.N-1)].
If EL2 is implemented and HDCR.HPMN is less than PMCR_EL0.N, this bit does not affect the operation of event counters in the range [HDCR.HPMN..(PMCR_EL0.N-1)].
The effect of MDCR_EL2.HPMN or HDCR.HPMN on the operation of this bit always applies if EL2 is implemented, at all Exception levels including EL2 and EL3, and regardless of whether EL2 is enabled in the current Security state. For more information, see the description of MDCR_EL2.HPMN or HDCR.HPMN.
If the highest implemented Exception level is using AArch32, it is IMPLEMENTATION DEFINED whether this bit is RW or RAZ/WI.
Otherwise:
Otherwise:
Reserved, RES0.
LC, bit [6]
When AArch32 is supported at any Exception level:
When AArch32 is supported at any Exception level:
Long cycle counter enable. Determines when unsigned overflow is recorded by the cycle counter overflow bit.
| LC | Meaning |
|---|---|
| 0b0 |
Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[31:0]. |
| 0b1 |
Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[63:0]. |
Arm deprecates use of PMCR_EL0.LC = 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES1.
DP, bit [5]
When EL3 is implemented or (FEAT_PMUv3p1 is implemented and EL2 is implemented):
When EL3 is implemented or (FEAT_PMUv3p1 is implemented and EL2 is implemented):
Disable cycle counter when event counting is prohibited. The possible values of this bit are:
| DP | Meaning |
|---|---|
| 0b0 |
Cycle counting by PMCCNTR_EL0 is not affected by this bit. |
| 0b1 |
When event counting for counters in the range [0..(MDCR_EL2.HPMN-1)] is prohibited, cycle counting by PMCCNTR_EL0 is disabled. |
For more information, see 'Prohibiting event counting'.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field it resets to:
- A value that is architecturally UNKNOWN if the reset is into an Exception level that is using AArch64.
- 0 if the reset is into an Exception level that is using AArch32.
Otherwise:
Otherwise:
Reserved, RES0.
X, bit [4]
When the implementation includes a PMU event export bus:
When the implementation includes a PMU event export bus:
Enable export of events in an IMPLEMENTATION DEFINED PMU event export bus.
| X | Meaning |
|---|---|
| 0b0 |
Do not export events. |
| 0b1 |
Export events where not prohibited. |
This field enables the exporting of events over an IMPLEMENTATION DEFINED PMU event export bus to another device, for example to an OPTIONAL PE trace unit.
No events are exported when counting is prohibited.
This field does not affect the generation of Performance Monitors overflow interrupt requests or signaling to a cross-trigger interface (CTI) that can be implemented as signals exported from the PE.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field it resets to:
- A value that is architecturally UNKNOWN if the reset is into an Exception level that is using AArch64.
- 0 if the reset is into an Exception level that is using AArch32.
Otherwise:
Otherwise:
Reserved, RAZ/WI.
D, bit [3]
When AArch32 is supported at any Exception level:
When AArch32 is supported at any Exception level:
Clock divider.
| D | Meaning |
|---|---|
| 0b0 |
When enabled, PMCCNTR_EL0 counts every clock cycle. |
| 0b1 |
When enabled, PMCCNTR_EL0 counts once every 64 clock cycles. |
If PMCR_EL0.LC == 1, this bit is ignored and the cycle counter counts every clock cycle.
Arm deprecates use of PMCR_EL0.D = 1.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field it resets to:
- A value that is architecturally UNKNOWN if the reset is into an Exception level that is using AArch64.
- 0 if the reset is into an Exception level that is using AArch32.
Otherwise:
Otherwise:
Reserved, RES0.
C, bit [2]
Cycle counter reset. The effects of writing to this bit are:
| C | Meaning |
|---|---|
| 0b0 |
No action. |
| 0b1 |
Reset PMCCNTR_EL0 to zero. |
This bit is always RAZ.
Resetting PMCCNTR_EL0 does not change the cycle counter overflow bit.
Access to this field is WO.
P, bit [1]
Event counter reset. The effects of writing to this bit are:
| P | Meaning |
|---|---|
| 0b0 |
No action. |
| 0b1 |
Reset all event counters, not including PMCCNTR_EL0, to zero. |
This bit is always RAZ.
Resetting the event counters does not change the event counter overflow bits.
If FEAT_PMUv3p5 is implemented, the value of MDCR_EL2.HLP, or PMCR_EL0.LP is ignored and bits [63:0] of all event counters are reset.
Access to this field is WO.
E, bit [0]
Enable.
| E | Meaning |
|---|---|
| 0b0 |
All event counters in the range [0..(PMN-1)] and PMCCNTR_EL0, are disabled. |
| 0b1 |
All event counters in the range [0..(PMN-1)] and PMCCNTR_EL0, are enabled by PMCNTENSET_EL0. |
If EL2 is implemented then:
- If EL2 is using AArch32, PMN is HDCR.HPMN.
- If EL2 is using AArch64, PMN is MDCR_EL2.HPMN.
- If PMN is less than PMCR_EL0.N, this bit does not affect the operation of event counters in the range [PMN..(PMCR_EL0.N-1)].
If EL2 is not implemented, PMN is PMCR_EL0.N.
The effect of the following fields on the operation of this bit applies if EL2 is implemented regardless of whether EL2 is enabled in the current Security state:
On a Warm reset, this field resets to 0.
Accessing the PMCR_EL0
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
PMCR_EL0 can be accessed through the external debug interface:
| Component | Offset | Instance |
|---|---|---|
| PMU | 0xE04 | PMCR_EL0 |
This interface is accessible as follows:
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus(), AllowExternalPMUAccess() and SoftwareLockStatus() accesses to this register are RO.
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus(), AllowExternalPMUAccess() and !SoftwareLockStatus() accesses to this register are RW.
- Otherwise accesses to this register generate an error response.