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ATS12NSOPW, Address Translate Stages 1 and 2 Non-secure Only PL1 Write
The ATS12NSOPW characteristics are:
Purpose
Performs stage 1 and 2 address translations as defined for PL1 and the Non-secure state, with permissions as if writing to the given virtual address.
Configuration
This instruction is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ATS12NSOPW are UNDEFINED.
Attributes
ATS12NSOPW is a 32-bit System instruction.
Field descriptions
The ATS12NSOPW input value bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Input address for translation | |||||||||||||||||||||||||||||||
Bits [31:0]
Input address for translation. The resulting address can be read from the PAR.
This System instruction takes a VA as input. The resulting address is the PA that is the output address of the stage 2 translation.
Executing the ATS12NSOPW instruction
Accesses to this instruction use the following encodings:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0111 | 0b1000 | 0b101 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif !ELUsingAArch32(EL2) && SCR_EL3.<NS,EEL2> == '01' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
ATS12NSOPW(R[t]);
elsif PSTATE.EL == EL3 then
ATS12NSOPW(R[t]);