DCCIMVAC, Data Cache line Clean and Invalidate by VA to PoC
The DCCIMVAC characteristics are:
Purpose
Clean and Invalidate data or unified cache line by virtual address to PoC.
Configuration
AArch32 System instruction DCCIMVAC performs the same function as AArch64 System instruction DC CIVAC.
This instruction is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to DCCIMVAC are UNDEFINED.
Attributes
DCCIMVAC is a 32-bit System instruction.
Field descriptions
The DCCIMVAC input value bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Virtual address to use | |||||||||||||||||||||||||||||||
Bits [31:0]
Virtual address to use. No alignment restrictions apply to this VA.
Executing the DCCIMVAC instruction
Execution of this instruction might require an address translation from VA to PA, and that translation might fault. For more information, see 'AArch32 data cache maintenance instructions (DC*)'.
Accesses to this instruction use the following encodings:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0111 | 0b1110 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TPCP == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TPC == '1' then
AArch32.TakeHypTrapException(0x03);
else
DCCIMVAC(R[t]);
elsif PSTATE.EL == EL2 then
DCCIMVAC(R[t]);
elsif PSTATE.EL == EL3 then
DCCIMVAC(R[t]);