ICIALLU, Instruction Cache Invalidate All to PoU
The ICIALLU characteristics are:
Purpose
Invalidate all instruction caches to PoU. If branch predictors are architecturally visible, also flush branch predictors.
Configuration
AArch32 System instruction ICIALLU performs the same function as AArch64 System instruction IC IALLU.
This instruction is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ICIALLU are UNDEFINED.
Attributes
ICIALLU is a 32-bit System instruction.
Field descriptions
This instruction has no applicable fields.
The value in the register specified by <Rt> is ignored.
Executing the ICIALLU instruction
The PE ignores the value of <Rt>. Software does not have to write a value to this register before issuing this instruction.
When HCR.FB is 1, at Non-secure EL1 this instruction executes as a ICIALLUIS.
Accesses to this instruction use the following encodings:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0111 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TPU == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TOCU == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TPU == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR2.TOCU == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.FB == '1' then
ICIALLUIS();
else
ICIALLU();
elsif PSTATE.EL == EL2 then
ICIALLU();
elsif PSTATE.EL == EL3 then
ICIALLU();