FPCR, Floatingpoint Control Register
The FPCR characteristics are:
Purpose
Controls floatingpoint behavior.
Configuration
The named fields in this register map to the equivalent fields in the AArch32 FPSCR.
It is IMPLEMENTATION DEFINED whether the Len and Stride fields can be programmed to nonzero values, which will cause some AArch32 floatingpoint instruction encodings to be UNDEFINED, or whether these fields are RAZ.
Attributes
FPCR is a 64bit register.
Field descriptions
The FPCR bit assignments are:
63  62  61  60  59  58  57  56  55  54  53  52  51  50  49  48  47  46  45  44  43  42  41  40  39  38  37  36  35  34  33  32 
RES0  
RES0  AHP  DN  FZ  RMode  Stride  FZ16  Len  IDE  RES0  IXE  UFE  OFE  DZE  IOE  RES0  NEP  AH  FIZ  
31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0 
Bits [63:27]
Reserved, RES0.
AHP, bit [26]
Alternative halfprecision control bit.
AHP  Meaning 

0b0 
IEEE halfprecision format selected. 
0b1 
Alternative halfprecision format selected. 
This bit is used only for conversions between halfprecision floatingpoint and other floatingpoint formats.
The dataprocessing instructions added as part of the FEAT_FP16 extension always use the IEEE halfprecision format, and ignore the value of this bit.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
DN, bit [25]
Default NaN mode control bit.
DN  Meaning 

0b0 
NaN operands propagate through to the output of a floatingpoint operation. 
0b1  Any operation involving one or more NaNs returns the Default NaN. If FPCR.AH is 1, this bit has no effect on the output of the FMAX, FMAXP, FMAXV, FMIN, FMINP, and FMINV instructions, and a default NaN is never returned as a result of these instructions. 
The value of this bit controls both scalar and Advanced SIMD floatingpoint arithmetic.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
FZ, bit [24]
Flushtozero mode control bit.
FZ  Meaning 

0b0 
Flushtozero mode disabled. Behavior of the floatingpoint system is fully compliant with the IEEE 754 standard. 
0b1  Flushtozero mode enabled. If FPCR.AH is 1:

The value of this bit controls both scalar and Advanced SIMD floatingpoint arithmetic.
This bit has no effect on halfprecision calculations.
If the result of an FMAX, FMAXP, FMAXV, FMIN, FMINP, or FMINV instruction is a denormalized number, it is not flushed to zero, regardless of the value of this bit.
Denormalized outputs of the following instructions, as determined after rounding with an unbounded exponent, are not affected by the value of this bit:

The BFCVT, BFCVTN, BFCVTN2, BFCVTNT, BFMLALB, and BFMLALT instructions.

Singleprecision and doubleprecision FRECPE, FRECPS, FRECPX, FRSQRTE, and FRSQRTS instructions.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
RMode, bits [23:22]
Rounding Mode control field.
RMode  Meaning 

0b00 
Round to Nearest (RN) mode. 
0b01 
Round towards Plus Infinity (RP) mode. 
0b10 
Round towards Minus Infinity (RM) mode. 
0b11 
Round towards Zero (RZ) mode. 
The specified rounding mode is used by both scalar and Advanced SIMD floatingpoint instructions.
If FPCR.AH is 1, then the following instructions use Round to Nearest mode regardless of the value of this bit:

The FRECPE, FRECPS, FRECPX, FRSQRTE, and FRSQRTS instructions.

The BFCVT, BFCVTN, BFCVTN2, BFCVTNT, BFMLALB, and BFMLALT instructions.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Stride, bits [21:20]
This field has no function in AArch64 state, and nonzero values are ignored during execution in AArch64 state.
This field is included only for context saving and restoration of the AArch32 FPSCR.Stride field.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
FZ16, bit [19]
When FEAT_FP16 is implemented:
When FEAT_FP16 is implemented:
Flushtozero mode control bit on halfprecision dataprocessing instructions.
FZ16  Meaning 

0b0 
Flushtozero mode disabled. Behavior of the floatingpoint system is fully compliant with the IEEE 754 standard. 
0b1  Flushtozero mode enabled. If FPCR.AH is 1:

The value of this bit applies to both scalar and Advanced SIMD floatingpoint halfprecision calculations. A halfprecision floatingpoint number that is flushed to zero as a result of the value of the FZ16 bit does not generate an Input Denormal exception.
If the result of an FMAX, FMAXP, FMAXV, FMIN, FMINP, or FMINV instruction is a denormalized number, it is not flushed to zero, regardless of the value of this bit.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
Len, bits [18:16]
This field has no function in AArch64 state, and nonzero values are ignored during execution in AArch64 state.
This field is included only for context saving and restoration of the AArch32 FPSCR.Len field.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
IDE, bit [15]
Input Denormal floatingpoint exception trap enable.
IDE  Meaning 

0b0 
Untrapped exception handling selected. If the floatingpoint exception occurs, the FPSR.IDC bit is set to 1. 
0b1 
Trapped exception handling selected. If the floatingpoint exception occurs, the PE does not update the FPSR.IDC bit. 
The value of this bit controls both scalar and Advanced SIMD floatingpoint arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [14:13]
Reserved, RES0.
IXE, bit [12]
Inexact floatingpoint exception trap enable.
IXE  Meaning 

0b0 
Untrapped exception handling selected. If the floatingpoint exception occurs, the FPSR.IXC bit is set to 1. 
0b1 
Trapped exception handling selected. If the floatingpoint exception occurs, the PE does not update the FPSR.IXC bit. 
The value of this bit controls both scalar and Advanced SIMD floatingpoint arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
UFE, bit [11]
Underflow floatingpoint exception trap enable.
UFE  Meaning 

0b0 
Untrapped exception handling selected. If the floatingpoint exception occurs, the FPSR.UFC bit is set to 1. 
0b1 
Trapped exception handling selected. If the floatingpoint exception occurs and Flushtozero is not enabled, the PE does not update the FPSR.UFC bit. 
The value of this bit controls both scalar and Advanced SIMD floatingpoint arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
OFE, bit [10]
Overflow floatingpoint exception trap enable.
OFE  Meaning 

0b0 
Untrapped exception handling selected. If the floatingpoint exception occurs, the FPSR.OFC bit is set to 1. 
0b1 
Trapped exception handling selected. If the floatingpoint exception occurs, the PE does not update the FPSR.OFC bit. 
The value of this bit controls both scalar and Advanced SIMD floatingpoint arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
DZE, bit [9]
Divide by Zero floatingpoint exception trap enable.
DZE  Meaning 

0b0 
Untrapped exception handling selected. If the floatingpoint exception occurs, the FPSR.DZC bit is set to 1. 
0b1 
Trapped exception handling selected. If the floatingpoint exception occurs, the PE does not update the FPSR.DZC bit. 
The value of this bit controls both scalar and Advanced SIMD floatingpoint arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
IOE, bit [8]
Invalid Operation floatingpoint exception trap enable.
IOE  Meaning 

0b0 
Untrapped exception handling selected. If the floatingpoint exception occurs, the FPSR.IOC bit is set to 1. 
0b1 
Trapped exception handling selected. If the floatingpoint exception occurs, the PE does not update the FPSR.IOC bit. 
The value of this bit controls both scalar and Advanced SIMD floatingpoint arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [7:3]
Reserved, RES0.
NEP, bit [2]
When FEAT_AFP is implemented:
When FEAT_AFP is implemented:
Controls how the output elements other than the lowest element of the vector are determined for Advanced SIMD scalar instructions.
NEP  Meaning 

0b0 
Does not affect how the output elements other than the lowest are determined for Advanced SIMD scalar instructions. 
0b1  The output elements other than the lowest are taken from the following registers:

On a Warm reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
AH, bit [1]
When FEAT_AFP is implemented:
When FEAT_AFP is implemented:
Alternate Handling. Controls alternate handling of denormalized floatingpoint numbers.
AH  Meaning 

0b0 
Does not affect handling of denormalized floatingpoint numbers. 
0b1  The signbit of the default NaN encoding is set to 1. For all floatingpoint instructions other than BFDOT and BFMMLA, detection of underflow occurs after rounding with an unbounded exponent. If an operation, other than FMAX, FMAXP, FMAXV, FMIN, FMINP, and FMINV, has two floatingpoint inputs in the <Vn>, <Hn>, <Sn>, or <Dn> register or the <Vm>, <Hm>, <Sm>, or <Dm> register, and two NaN inputs, then the output is derived from the NaN held in the <Vn>, <Hn>, <Sn>, or <Dn> register, regardless of whether any input is a signaling NaN or a quiet NaN. For the BFMLALB, BFMLALT, FCMLA, FMADD, FMLA, FMLAL, FMLAL2, FMLS, FMLSL, FMLSL2, FMSUB, FNMADD, and FNMSUB instructions, regardless of whether any input is a signaling NaN or a quiet NaN:
The FMAX, FMAXP, FMAXV, FMIN, FMINP, and FMINV instructions change their algorithm to calculate the minimum and maximum so that:
The FCVTAS, FCVTAU, FCVTMS, FCVTMU, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTZS, FCVTZU, FJCVTZS, FRINT32X, FRINT32Z, FRINT64X, FRINT64Z, FRINTA, FRINTI, FRINTM, FRINTN, FRINTP, FRINTX, and FRINTZ instructions never generate an Input Denormal floatingpoint exception. The BFCVT, BFCVTN, BFCVTN2, BFCVTNT, BFMLALB, and BFMLALT instructions:
The FRECPE, FRECPS, FRECPX, FRSQRTE, and FRSQRTS instructions:
When the output is flushed to zero:
If FPCR.FZ is 1, this does not cause any Input Denormal exceptions and does not cause input denormal operands to be flushed to zero. If FPCR.FIZ is 0, any operation that unpacks a denormalized floatingpoint number, other than a BFloat or halfprecision number, will generate an Input Denormal floatingpoint exception, except when:

On a Warm reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
FIZ, bit [0]
When FEAT_AFP is implemented:
When FEAT_AFP is implemented:
Flush Inputs to Zero. Controls whether singleprecision, doubleprecision, and BFloat16 input operands that are denormalized numbers are flushed to zero.
FIZ  Meaning 

0b0  If FPCR.AH is 0, does not affect whether denormalized floatingpoint inputs are flushed to zero. If FPCR.AH is 1, any operation that unpacks a singleprecision or doubleprecision denormalized floatingpoint number will generate an Input Denormal floatingpoint exception, except when:

0b1  All singleprecision, doubleprecision, and BFloat16 input operands that are denormalized numbers, except FABS and FNEG, are flushed to zero, retaining the sign. If FPCR.AH is 1 or FPCR.FZ is 0, denormalized numbers that are flushed to zero by this field do not generate an Input Denormal exception. 
The following instructions are not affected by the value of this bit:

The BFCVT, BFCVTN, BFCVTN2, BFCVTNT, BFMLALB, and BFMLALT instructions.

Singleprecision and doubleprecision variants of the FRECPE, FRECPS, FRECPX, FRSQRTE, and FRSQRTS instructions.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
Accessing the FPCR
Accesses to this register use the following encodings:
MRS <Xt>, FPCR
op0  op1  CRn  CRm  op2 

0b11  0b011  0b0100  0b0100  0b000 
if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.FPEN != '11' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x00); else AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.FPEN != '11' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else return FPCR; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif CPACR_EL1.FPEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else return FPCR; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else return FPCR; elsif PSTATE.EL == EL3 then if CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else return FPCR;
MSR FPCR, <Xt>
op0  op1  CRn  CRm  op2 

0b11  0b011  0b0100  0b0100  0b000 
if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.FPEN != '11' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x00); else AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.FPEN != '11' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else FPCR = X[t]; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif CPACR_EL1.FPEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else FPCR = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else FPCR = X[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else FPCR = X[t];