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FPCR, Floating-point Control Register

The FPCR characteristics are:

Purpose

Controls floating-point behavior.

Configuration

The named fields in this register map to the equivalent fields in the AArch32 FPSCR.

It is IMPLEMENTATION DEFINED whether the Len and Stride fields can be programmed to non-zero values, which will cause some AArch32 floating-point instruction encodings to be UNDEFINED, or whether these fields are RAZ.

Attributes

FPCR is a 64-bit register.

Field descriptions

The FPCR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0AHPDNFZRModeStrideFZ16LenIDERES0IXEUFEOFEDZEIOERES0NEPAHFIZ
313029282726252423222120191817161514131211109876543210

Bits [63:27]

Reserved, RES0.

AHP, bit [26]

Alternative half-precision control bit.

AHPMeaning
0b0

IEEE half-precision format selected.

0b1

Alternative half-precision format selected.

This bit is used only for conversions between half-precision floating-point and other floating-point formats.

The data-processing instructions added as part of the FEAT_FP16 extension always use the IEEE half-precision format, and ignore the value of this bit.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

DN, bit [25]

Default NaN mode control bit.

DNMeaning
0b0

NaN operands propagate through to the output of a floating-point operation.

0b1

Any operation involving one or more NaNs returns the Default NaN.

If FPCR.AH is 1, this bit has no effect on the output of the FMAX, FMAXP, FMAXV, FMIN, FMINP, and FMINV instructions, and a default NaN is never returned as a result of these instructions.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

FZ, bit [24]

Flush-to-zero mode control bit.

FZMeaning
0b0

Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.

0b1

Flush-to-zero mode enabled.

If FPCR.AH is 1:

  • This bit does not generate Input Denormal exceptions.

  • This bit does not cause input denormal operands to be flushed to zero.

  • When the output is flushed to zero:

    • An Inexact floating-point exception is generated.

    • The test for a denormalized number for half-precision, single-precision, and double-precision numbers occurs after rounding with an unbounded exponent.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

This bit has no effect on half-precision calculations.

If the result of an FMAX, FMAXP, FMAXV, FMIN, FMINP, or FMINV instruction is a denormalized number, it is not flushed to zero, regardless of the value of this bit.

Denormalized outputs of the following instructions, as determined after rounding with an unbounded exponent, are not affected by the value of this bit:

  • The BFCVT, BFCVTN, BFCVTN2, BFCVTNT, BFMLALB, and BFMLALT instructions.

  • Single-precision and double-precision FRECPE, FRECPS, FRECPX, FRSQRTE, and FRSQRTS instructions.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

RMode, bits [23:22]

Rounding Mode control field.

RModeMeaning
0b00

Round to Nearest (RN) mode.

0b01

Round towards Plus Infinity (RP) mode.

0b10

Round towards Minus Infinity (RM) mode.

0b11

Round towards Zero (RZ) mode.

The specified rounding mode is used by both scalar and Advanced SIMD floating-point instructions.

If FPCR.AH is 1, then the following instructions use Round to Nearest mode regardless of the value of this bit:

  • The FRECPE, FRECPS, FRECPX, FRSQRTE, and FRSQRTS instructions.

  • The BFCVT, BFCVTN, BFCVTN2, BFCVTNT, BFMLALB, and BFMLALT instructions.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Stride, bits [21:20]

This field has no function in AArch64 state, and non-zero values are ignored during execution in AArch64 state.

This field is included only for context saving and restoration of the AArch32 FPSCR.Stride field.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

FZ16, bit [19]

When FEAT_FP16 is implemented:

Flush-to-zero mode control bit on half-precision data-processing instructions.

FZ16Meaning
0b0

Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.

0b1

Flush-to-zero mode enabled.

If FPCR.AH is 1:

  • When the output is flushed to zero:

    • An Inexact floating-point exception is generated.

    • The test for a denormalized number for half-precision, single-precision, and double-precision numbers occurs after rounding with an unbounded exponent.

The value of this bit applies to both scalar and Advanced SIMD floating-point half-precision calculations. A half-precision floating-point number that is flushed to zero as a result of the value of the FZ16 bit does not generate an Input Denormal exception.

If the result of an FMAX, FMAXP, FMAXV, FMIN, FMINP, or FMINV instruction is a denormalized number, it is not flushed to zero, regardless of the value of this bit.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Len, bits [18:16]

This field has no function in AArch64 state, and non-zero values are ignored during execution in AArch64 state.

This field is included only for context saving and restoration of the AArch32 FPSCR.Len field.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

IDE, bit [15]

Input Denormal floating-point exception trap enable.

IDEMeaning
0b0

Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.IDC bit is set to 1.

0b1

Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IDC bit.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RAZ/WI.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [14:13]

Reserved, RES0.

IXE, bit [12]

Inexact floating-point exception trap enable.

IXEMeaning
0b0

Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.IXC bit is set to 1.

0b1

Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IXC bit.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RAZ/WI.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

UFE, bit [11]

Underflow floating-point exception trap enable.

UFEMeaning
0b0

Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.UFC bit is set to 1.

0b1

Trapped exception handling selected. If the floating-point exception occurs and Flush-to-zero is not enabled, the PE does not update the FPSR.UFC bit.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RAZ/WI.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

OFE, bit [10]

Overflow floating-point exception trap enable.

OFEMeaning
0b0

Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.OFC bit is set to 1.

0b1

Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.OFC bit.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RAZ/WI.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

DZE, bit [9]

Divide by Zero floating-point exception trap enable.

DZEMeaning
0b0

Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.DZC bit is set to 1.

0b1

Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.DZC bit.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RAZ/WI.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

IOE, bit [8]

Invalid Operation floating-point exception trap enable.

IOEMeaning
0b0

Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.IOC bit is set to 1.

0b1

Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IOC bit.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RAZ/WI.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [7:3]

Reserved, RES0.

NEP, bit [2]

When FEAT_AFP is implemented:

Controls how the output elements other than the lowest element of the vector are determined for Advanced SIMD scalar instructions.

NEPMeaning
0b0

Does not affect how the output elements other than the lowest are determined for Advanced SIMD scalar instructions.

0b1

The output elements other than the lowest are taken from the following registers:

  • For 3-input scalar versions of the FMLA (by element) and FMLS (by element) instructions, the <Hd>, <Sd>, or <Dd> register.

  • For 3-input versions of the FMADD, FMSUB, FNMADD, and FNMSUB instructions, the <Ha>, <Sa>, or <Da> register.

  • For 2-input scalar versions of the FACGE, FACGT, FCMEQ (register), FCMGE (register), and FCMGT (register) instructions, the <Hm>, <Sm>, or <Dm> register.

  • For 2-input scalar versions of the FABD, FADD (scalar), FDIV (scalar), FMAX (scalar), FMAXNM (scalar), FMIN (scalar), FMINNM (scalar), FMUL (by element), FMUL (scalar), FMULX, FNMUL (scalar), FRECPS, FRSQRTS, and FSUB (scalar) instructions, the <Hn>, <Sn>, or <Dn> register.

  • For 1-input scalar versions of the following instructions, the <Hd>, <Sd>, or <Dd> register:

    • The (vector) versions of the FCVTAS, FCVTAU, FCVTMS, FCVTMU, FCVTNS, FCVTNU, FCVTPS, and FCVTPU instructions.

    • The (vector, fixed-point) and (vector, integer) versions of the FCVTZS, FCVTZU, SCVTF, and UCVTF instructions.

    • The (scalar) versions of the FABS, FNEG, FRINT32X, FRINT32Z, FRINT64X, FRINT64Z, FRINTA, FRINTI, FRINTM, FRINTN, FRINTP, FRINTX, FRINTZ, and FSQRT instructions.

    • The (scalar, fixed-point) and (scalar, integer) versions of the SCVTF and UCVTF instructions.

    • The BFCVT, FCVT, FCVTXN, FRECPE, FRECPX, and FRSQRTE instructions.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

AH, bit [1]

When FEAT_AFP is implemented:

Alternate Handling. Controls alternate handling of denormalized floating-point numbers.

AHMeaning
0b0

Does not affect handling of denormalized floating-point numbers.

0b1

The sign-bit of the default NaN encoding is set to 1.

For all floating-point instructions other than BFDOT and BFMMLA, detection of underflow occurs after rounding with an unbounded exponent.

If an operation, other than FMAX, FMAXP, FMAXV, FMIN, FMINP, and FMINV, has two floating-point inputs in the <Vn>, <Hn>, <Sn>, or <Dn> register or the <Vm>, <Hm>, <Sm>, or <Dm> register, and two NaN inputs, then the output is derived from the NaN held in the <Vn>, <Hn>, <Sn>, or <Dn> register, regardless of whether any input is a signaling NaN or a quiet NaN.

For the BFMLALB, BFMLALT, FCMLA, FMADD, FMLA, FMLAL, FMLAL2, FMLS, FMLSL, FMLSL2, FMSUB, FNMADD, and FNMSUB instructions, regardless of whether any input is a signaling NaN or a quiet NaN:

  • If the operation has three NaN inputs, then the output is derived from the NaN held in the <Vn>, <Hn>, <Sn>, or <Dn> register.

  • If the operation has two NaN inputs and the <Vn>, <Hn>, <Sn>, or <Dn> register holds a NaN, then the output is derived from the NaN held in that register.

  • If the operation has two NaN inputs and the <Vn>, <Hn>, <Sn>, or <Dn> register does not hold a NaN, then the output is derived from the NaN held in the <Hm>, <Sm>, or <Dm> register.

The FMAX, FMAXP, FMAXV, FMIN, FMINP, and FMINV instructions change their algorithm to calculate the minimum and maximum so that:

  • If the result is a denormalized number, it is not flushed to zero, regardless of FPCR.FZ or FPCR.FZ16.

  • If either input is a quiet NaN or a signaling NaN, then the second operand is returned as the result of the instruction and an Invalid Operation floating-point exception is generated.

  • If the two operands are +0 and -0 in any order, the second operand of the instruction is returned as the result of the instruction.

  • FPCR.DN has no effect on the output and a default NaN is never returned as the result of the instruction.

The FCVTAS, FCVTAU, FCVTMS, FCVTMU, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTZS, FCVTZU, FJCVTZS, FRINT32X, FRINT32Z, FRINT64X, FRINT64Z, FRINTA, FRINTI, FRINTM, FRINTN, FRINTP, FRINTX, and FRINTZ instructions never generate an Input Denormal floating-point exception.

The BFCVT, BFCVTN, BFCVTN2, BFCVTNT, BFMLALB, and BFMLALT instructions:

  • Use Round to Nearest rounding mode, regardless of the rounding mode selected in FPCR.RMode.

  • Flush all denormalized inputs to zero, retaining the sign, regardless of FPCR.FIZ.

  • Flush all denormalized outputs, as determined after rounding with an unbounded exponent, to zero, retaining the sign, regardless of FPCR.FZ.

  • Do not generate any floating-point exceptions, regardless of their input or output values.

The FRECPE, FRECPS, FRECPX, FRSQRTE, and FRSQRTS instructions:

  • Use Round to Nearest rounding mode, regardless of the rounding mode selected in FPCR.RMode.

  • Do not generate any floating-point exceptions.

  • The single-precision and double-precision variants of these instructions:

    • Flush all denormalized inputs to zero, retaining the sign, regardless of FPCR.FIZ.

    • Flush all denormalized outputs, as determined after rounding with an unbounded exponent, to zero, retaining the sign, regardless of FPCR.FZ.

When the output is flushed to zero:

  • An Inexact floating-point exception is generated.

  • The test for a denormalized number for half-precision, single-precision, and double-precision numbers occurs after rounding with an unbounded exponent.

If FPCR.FZ is 1, this does not cause any Input Denormal exceptions and does not cause input denormal operands to be flushed to zero.

If FPCR.FIZ is 0, any operation that unpacks a denormalized floating-point number, other than a BFloat or half-precision number, will generate an Input Denormal floating-point exception, except when:

  • One of the other operands of the instruction is a NaN.

  • The operation also generates an Invalid Operation floating-point exception or a Divide by Zero floating-point exception.

  • The operation was generated by a BFCVT, BFCVTN, BFCVTN2, or BFCVTNT instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

FIZ, bit [0]

When FEAT_AFP is implemented:

Flush Inputs to Zero. Controls whether single-precision, double-precision, and BFloat16 input operands that are denormalized numbers are flushed to zero.

FIZMeaning
0b0

If FPCR.AH is 0, does not affect whether denormalized floating-point inputs are flushed to zero.

If FPCR.AH is 1, any operation that unpacks a single-precision or double-precision denormalized floating-point number will generate an Input Denormal floating-point exception, except when:

  • One of the other operands of the instruction is a NaN.

  • The operation also generates an Invalid Operation floating-point exception or a Divide by Zero floating-point exception.

  • The operation was generated by a BFCVTN, BFCVTN2, BFCVT, or a BFCVTNT instruction.

0b1

All single-precision, double-precision, and BFloat16 input operands that are denormalized numbers, except FABS and FNEG, are flushed to zero, retaining the sign.

If FPCR.AH is 1 or FPCR.FZ is 0, denormalized numbers that are flushed to zero by this field do not generate an Input Denormal exception.

The following instructions are not affected by the value of this bit:

  • The BFCVT, BFCVTN, BFCVTN2, BFCVTNT, BFMLALB, and BFMLALT instructions.

  • Single-precision and double-precision variants of the FRECPE, FRECPS, FRECPX, FRSQRTE, and FRSQRTS instructions.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Accessing the FPCR

Accesses to this register use the following encodings:

MRS <Xt>, FPCR

op0op1CRnCRmop2
0b110b0110b01000b01000b000
if PSTATE.EL == EL0 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then
        UNDEFINED;
    elsif !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.FPEN != '11' then
        if EL2Enabled() && HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x00);
        else
            AArch64.SystemAccessTrap(EL1, 0x07);
    elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.FPEN != '11' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x07);
    else
        return FPCR;
elsif PSTATE.EL == EL1 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then
        UNDEFINED;
    elsif CPACR_EL1.FPEN == 'x0' then
        AArch64.SystemAccessTrap(EL1, 0x07);
    elsif EL2Enabled() && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x07);
    else
        return FPCR;
elsif PSTATE.EL == EL2 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then
        UNDEFINED;
    elsif HCR_EL2.E2H == '0' && CPTR_EL2.TFP == '1' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x07);
    else
        return FPCR;
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TFP == '1' then
        AArch64.SystemAccessTrap(EL3, 0x07);
    else
        return FPCR;
              

MSR FPCR, <Xt>

op0op1CRnCRmop2
0b110b0110b01000b01000b000
if PSTATE.EL == EL0 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then
        UNDEFINED;
    elsif !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.FPEN != '11' then
        if EL2Enabled() && HCR_EL2.TGE == '1' then
            AArch64.SystemAccessTrap(EL2, 0x00);
        else
            AArch64.SystemAccessTrap(EL1, 0x07);
    elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.FPEN != '11' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x07);
    else
        FPCR = X[t];
elsif PSTATE.EL == EL1 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then
        UNDEFINED;
    elsif CPACR_EL1.FPEN == 'x0' then
        AArch64.SystemAccessTrap(EL1, 0x07);
    elsif EL2Enabled() && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x07);
    else
        FPCR = X[t];
elsif PSTATE.EL == EL2 then
    if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then
        UNDEFINED;
    elsif HCR_EL2.E2H == '0' && CPTR_EL2.TFP == '1' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then
        AArch64.SystemAccessTrap(EL2, 0x07);
    elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then
        if Halted() && EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x07);
    else
        FPCR = X[t];
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TFP == '1' then
        AArch64.SystemAccessTrap(EL3, 0x07);
    else
        FPCR = X[t];