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CNTNSAR, Counter-timer Non-secure Access Register

The CNTNSAR characteristics are:

Purpose

Provides the highest-level control of whether frames CNTBaseN and CNTEL0BaseN are accessible by Non-secure accesses.

Configuration

The power domain of CNTNSAR is IMPLEMENTATION DEFINED.

For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.

Attributes

CNTNSAR is a 32-bit register.

Field descriptions

The CNTNSAR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0NS7NS6NS5NS4NS3NS2NS1NS0

Bits [31:8]

Reserved, RES0.

NS<n>, bit [n], for n = 7 to 0

Non-secure access to frame n. The possible values of this bit are:

NS<n>Meaning
0b0

Secure access only. Behaves as RES0 to Non-secure accesses.

0b1

Secure and Non-secure accesses permitted.

This bit also determines whether, in the CNTCTLBase frame, CNTACR<n> and CNTVOFF<n> are accessible to Non-secure accesses.

If frame CNTBase<n>:

  • Is not implemented, then NS<n> is RES0.
  • Is not Configurable access, and is accessible only by Secure accesses, then NS<n> is RES0.
  • Is not Configurable access, and is accessible by both Secure and Non-secure accesses, then NS<n> is RES1.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing the CNTNSAR

In a system that recognizes two Security states, this register is only accessible by Secure accesses.

CNTNSAR can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
TimerCNTCTLBase0x004CNTNSAR

Accesses on this interface are RW.