EDECR, External Debug Execution Control Register

The EDECR characteristics are:

Purpose

Controls Halting debug events.

Configuration

If FEAT_DoPD is implemented, this register is in the Core power domain.

If FEAT_DoPD is not implemented, this register is in the Debug power domain.

Attributes

EDECR is a 32-bit register.

Field descriptions

The EDECR bit assignments are:

Bits [31:3]

Reserved, RES0.

SS, bit [2]

Halting step enable. Possible values of this field are:

If the value of EDECR.SS is changed when the PE is in Non-debug state, behavior is CONSTRAINED UNPREDICTABLE as described in 'Changing the value of EDECR.SS when not in Debug state'.

On a Cold reset, when FEAT_DoPD is implemented, this field resets to 0.

On an External debug reset, when FEAT_DoPD is not implemented, this field resets to 0.

RCE, bit [1]

When FEAT_DoPD is not implemented:

Reset Catch Enable.

On an External debug reset, this field resets to 0.

Otherwise:

Reserved, RES0.

OSUCE, bit [0]

When FEAT_DoPD is not implemented:

OS Unlock Catch Enable.

On an External debug reset, this field resets to 0.

Otherwise:

Reserved, RES0.

Accessing the EDECR

EDECR can be accessed through the external debug interface:

This interface is accessible as follows:

• When (FEAT_DoPD is not implemented or IsCorePowered()) and SoftwareLockStatus() accesses to this register are RO.
• When (FEAT_DoPD is not implemented or IsCorePowered()) and !SoftwareLockStatus() accesses to this register are RW.
• Otherwise accesses to this register generate an error response.