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EDITCTRL, External Debug Integration mode Control register

The EDITCTRL characteristics are:


Enables the external debug to switch from its default mode into integration mode, where test software can control directly the inputs and outputs of the PE, for integration testing or topology detection.


It is IMPLEMENTATION DEFINED whether EDITCTRL is implemented in the Core power domain or in the Debug power domain.

Implementation of this register is OPTIONAL.


EDITCTRL is a 32-bit register.

Field descriptions

The EDITCTRL bit assignments are:


Bits [31:1]

Reserved, RES0.

IME, bit [0]

Integration mode enable. When IME == 1, the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED.


Normal operation.


Integration mode enabled.

The following resets apply:

  • Whichever power domain the register is implemented in, this field resets to 0.

  • Otherwise, the value of this field is unchanged.

Accessing the EDITCTRL

EDITCTRL can be accessed through the external debug interface:


This interface is accessible as follows:

  • When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and SoftwareLockStatus() accesses to this register are RO.
  • When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and !SoftwareLockStatus() accesses to this register are RW.
  • Otherwise accesses to this register are IMPDEF.