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EDPIDR4, External Debug Peripheral Identification Register 4

The EDPIDR4 characteristics are:


Provides information to identify an external debug component.

For more information, see 'About the Peripheral identification scheme'.


Implementation of this register is OPTIONAL.

If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.

This register is required for CoreSight compliance.


EDPIDR4 is a 32-bit register.

Field descriptions

The EDPIDR4 bit assignments are:


Bits [31:8]

Reserved, RES0.

SIZE, bits [7:4]

Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers.

DES_2, bits [3:0]

Designer, JEP106 continuation code, least significant nibble. For Arm Limited, this field is 0b0100.

Accessing the EDPIDR4

EDPIDR4 can be accessed through the external debug interface:


This interface is accessible as follows:

  • When FEAT_DoPD is not implemented or IsCorePowered() accesses to this register are RO.
  • Otherwise accesses to this register generate an error response.