ERRFHICR0, Fault Handling Interrupt Configuration Register 0
The ERRFHICR0 characteristics are:
Fault Handling Interrupt configuration register.
This register is present only when (the Fault Handling Interrupt is implemented or the implementation does not use the recommended layout for the ERRIRQCR<n> registers) and interrupt configuration registers are implemented. Otherwise, direct accesses to ERRFHICR0 are RES0.
ERRFHICR0 is implemented only as part of a memory-mapped group of error records.
ERRFHICR0 is a 64-bit register.
The ERRFHICR0 bit assignments are:
When the Fault Handling Interrupt is implemented and the implementation uses the recommended layout for the ERRIRQCR<n> registers:
ADDR, bits [55:2]
Message Signaled Interrupt address. (ERRFHICR0.ADDR << 2) is the address that the component writes to when signaling the Fault Handling Interrupt. Bits [1:0] of the address are always zero.
The physical address size supported by the component is IMPLEMENTATION DEFINED. Unimplemented high-order physical address bits are RES0.
On an Error recovery reset, this field resets to an architecturally UNKNOWN value.
When the implementation does not use the recommended layout for the ERRIRQCR<n> registers:
IMPLEMENTATION DEFINED, bits [63:0]
Accessing the ERRFHICR0
ERRFHICR0 can be accessed through the memory-mapped interfaces:
Accesses on this interface are RW.