GICC_IIDR, CPU Interface Identification Register
The GICC_IIDR characteristics are:
Purpose
Provides information about the implementer and revision of the CPU interface.
Configuration
Attributes
GICC_IIDR is a 32-bit register.
Field descriptions
The GICC_IIDR bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ProductID | Architecture_version | Revision | Implementer | ||||||||||||||||||||||||||||
ProductID, bits [31:20]
An IMPLEMENTATION DEFINED product identifier.
Architecture_version, bits [19:16]
The version of the GIC architecture that is implemented.
| Architecture_version | Meaning |
|---|---|
| 0b0001 |
GICv1. |
| 0b0010 |
GICv2. |
| 0b0011 |
FEAT_GICv3 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1. |
| 0b0100 |
FEAT_GICv4 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1. |
Other values are reserved.
Revision, bits [15:12]
An IMPLEMENTATION DEFINED revision number for the CPU interface.
Implementer, bits [11:0]
Contains the JEP106 code of the company that implemented the CPU interface.
- Bits [11:8] are the JEP106 continuation code of the implementer. For an Arm implementation, this field is 0x4.
- Bit [7] is always 0.
- Bits [6:0] are the JEP106 identity code of the implementer. For an Arm implementation, bits [7:0] are therefore 0x3B.
Accessing the GICC_IIDR
GICC_IIDR can be accessed through the memory-mapped interfaces:
| Component | Offset | Instance |
|---|---|---|
| GIC CPU interface | 0x00FC | GICC_IIDR |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0 accesses to this register are RO.
- When an access is Secure accesses to this register are RO.
- When an access is Non-secure accesses to this register are RO.