GICC_STATUSR, CPU Interface Status Register

The GICC_STATUSR characteristics are:

Purpose

Provides software with a mechanism to detect:

• Accesses to reserved locations.
• Writes to read-only locations.
• Reads of write-only locations.

Configuration

If the GIC implementation supports two Security states this register is Banked to provide Secure and Non-secure copies.

This register is used only when System register access is not enabled. If System register access is enabled, this register is not updated. Equivalent functionality might be provided by appropriate traps and exceptions.

Attributes

GICC_STATUSR is a 32-bit register.

Field descriptions

The GICC_STATUSR bit assignments are:

Bits [31:5]

Reserved, RES0.

ASV, bit [4]

Attempted security violation.

WROD, bit [3]

Write to an RO location.

When a violation is detected, software must write 1 to this register to reset it.

RWOD, bit [2]

Read of a WO location.

When a violation is detected, software must write 1 to this register to reset it.

WRD, bit [1]

Write to a reserved location.

When a violation is detected, software must write 1 to this register to reset it.

RRD, bit [0]

Read of a reserved location.

When a violation is detected, software must write 1 to this register to reset it.

Accessing the GICC_STATUSR

This is an optional register. If the register is not implemented, the location is RAZ/WI.

If this register is implemented, GICV_STATUSR must also be implemented.

GICC_STATUSR can be accessed through the memory-mapped interfaces:

This interface is accessible as follows:

• When GICD_CTLR.DS == 0 accesses to this register are RW.
• When an access is Secure accesses to this register are RW.

This interface is accessible as follows:

• When GICD_CTLR.DS == 0 accesses to this register are RW.
• When an access is Non-secure accesses to this register are RW.